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Commit d978a636 authored by David S. Miller's avatar David S. Miller
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Conflicts:
	drivers/nfc/microread/mei.c
	net/netfilter/nfnetlink_queue_core.c

Pull in 'net' to get Eric Biederman's AF_UNIX fix, upon which
some cleanups are going to go on-top.

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 8303e699 cb28ea3b
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+2 −3
Original line number Diff line number Diff line
@@ -890,9 +890,8 @@ Prior to version 0.9.0rc4 options had a 'snd_' prefix. This was removed.
    enable_msi	- Enable Message Signaled Interrupt (MSI) (default = off)
    power_save	- Automatic power-saving timeout (in second, 0 =
		disable)
    power_save_controller - Support runtime D3 of HD-audio controller
		(-1 = on for supported chip (default), false = off,
		 true = force to on even for unsupported hardware)
    power_save_controller - Reset HD-audio controller in power-saving mode
		(default = on)
    align_buffer_size - Force rounding of buffer/period sizes to multiples
    		      of 128 bytes. This is more efficient in terms of memory
		      access but isn't required by the HDA spec and prevents
+0 −1
Original line number Diff line number Diff line
@@ -6953,7 +6953,6 @@ F: drivers/scsi/st*

SCTP PROTOCOL
M:	Vlad Yasevich <vyasevich@gmail.com>
M:	Sridhar Samudrala <sri@us.ibm.com>
M:	Neil Horman <nhorman@tuxdriver.com>
L:	linux-sctp@vger.kernel.org
W:	http://lksctp.sourceforge.net
+12 −2
Original line number Diff line number Diff line
@@ -1183,9 +1183,9 @@ config ARM_NR_BANKS
	default 8

config IWMMXT
	bool "Enable iWMMXt support"
	bool "Enable iWMMXt support" if !CPU_PJ4
	depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
	default y if PXA27x || PXA3xx || ARCH_MMP
	default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
	help
	  Enable support for iWMMXt context switching at run time if
	  running on a CPU that supports it.
@@ -1439,6 +1439,16 @@ config ARM_ERRATA_775420
	 to deadlock. This workaround puts DSB before executing ISB if
	 an abort may occur on cache maintenance.

config ARM_ERRATA_798181
	bool "ARM errata: TLBI/DSB failure on Cortex-A15"
	depends on CPU_V7 && SMP
	help
	  On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
	  adequately shooting down all use of the old entries. This
	  option enables the Linux kernel workaround for this erratum
	  which sends an IPI to the CPUs that are running the same ASID
	  as the one being invalidated.

endmenu

source "arch/arm/common/Kconfig"
+1 −1
Original line number Diff line number Diff line
@@ -24,7 +24,7 @@ extern struct arm_delay_ops {
	void (*delay)(unsigned long);
	void (*const_udelay)(unsigned long);
	void (*udelay)(unsigned long);
	bool const_clock;
	unsigned long ticks_per_jiffy;
} arm_delay_ops;

#define __delay(n)		arm_delay_ops.delay(n)
+7 −0
Original line number Diff line number Diff line
@@ -41,6 +41,13 @@ extern void kunmap_high(struct page *page);
#endif
#endif

/*
 * Needed to be able to broadcast the TLB invalidation for kmap.
 */
#ifdef CONFIG_ARM_ERRATA_798181
#undef ARCH_NEEDS_KMAP_HIGH_GET
#endif

#ifdef ARCH_NEEDS_KMAP_HIGH_GET
extern void *kmap_high_get(struct page *page);
#else
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