Merge tag 'pinctrl-v4.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

* Oxford Semiconductor OXNAS SoC GPIO Controller

Please refer to gpio.txt for generic information regarding GPIO bindings.

Required properties:

 - compatible: "oxsemi,ox810se-gpio"

 - reg: Base address and length for the device.

 - interrupts: The port interrupt shared by all pins.

 - gpio-controller: Marks the port as GPIO controller.

 - #gpio-cells: Two. The first cell is the pin number and

   the second cell is used to specify the gpio polarity as defined in

   defined in <dt-bindings/gpio/gpio.h>:

      0 = GPIO_ACTIVE_HIGH

      1 = GPIO_ACTIVE_LOW

 - interrupt-controller: Marks the device node as an interrupt controller.

 - #interrupt-cells: Two. The first cell is the GPIO number and second cell

   is used to specify the trigger type as defined in

   <dt-bindings/interrupt-controller/irq.h>:

      IRQ_TYPE_EDGE_RISING

      IRQ_TYPE_EDGE_FALLING

      IRQ_TYPE_EDGE_BOTH

 - gpio-ranges: Interaction with the PINCTRL subsystem, it also specifies the

   gpio base and count, should be in the format of numeric-gpio-range as

   specified in the gpio.txt file.

Example:

gpio0: gpio@0 {

	compatible = "oxsemi,ox810se-gpio";

	reg = <0x000000 0x100000>;

	interrupts = <21>;

	#gpio-cells = <2>;

	gpio-controller;

	interrupt-controller;

	#interrupt-cells = <2>;

	gpio-ranges = <&pinctrl 0 0 32>;

};

keys {

	...

	button-esc {

		label = "ESC";

		linux,code = <1>;

		gpios = <&gpio0 12 0>;

	};

};

Required properties:

- compatible:

    Must be "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio",

    "brcm,cygnus-crmu-gpio" or "brcm,iproc-gpio"

    "brcm,iproc-gpio" for the generic iProc based GPIO controller IP that

    supports full-featured pinctrl and GPIO functions used in various iProc

    based SoCs

    May contain an SoC-specific compatibility string to accommodate any

    SoC-specific features

    "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or

    "brcm,cygnus-crmu-gpio" for Cygnus SoCs

    "brcm,iproc-nsp-gpio" for the iProc NSP SoC that has drive strength support

    disabled

    "brcm,iproc-stingray-gpio" for the iProc Stingray SoC that has the general

    pinctrl support completely disabled in this IP block. In Stingray, a

    different IP block is used to handle pinctrl related functions

- reg:

    Define the base and range of the I/O address space that contains SoC

Broadcom NSP (Northstar plus) IOMUX Controller

The NSP IOMUX controller supports group based mux configuration. In

addition, certain pins can be muxed to GPIO function individually.

Required properties:

- compatible:

    Must be "brcm,nsp-pinmux"

- reg:

    Should contain the register physical address and length for each of

    GPIO_CONTROL0, GP_AUX_SEL and IPROC_CONFIG IOMUX registers

Properties in subnodes:

- function:

    The mux function to select

- groups:

    The list of groups to select with a given function

For more details, refer to

Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt

For example:

	pinmux: pinmux@1803f1c0 {

		compatible = "brcm,nsp-pinmux";

		reg = <0x1803f1c0 0x04>,

		      <0x18030028 0x04>,

		      <0x1803f408 0x04>;

		pinctrl-names = "default";

		pinctrl-0 = <&pwm &gpio_b &nand_sel>;

		pwm: pwm {

			function = "pwm";

			groups = "pwm0_grp", "pwm1_grp";

		};

		gpio_b: gpio_b {

			function = "gpio_b";

			groups = "gpio_b_0_grp", "gpio_b_1_grp";

		};

		nand_sel: nand_sel {

			function = "nand";

			groups = "nand_grp";

		};

	};

List of supported functions and groups in Northstar Plus:

"spi": "spi_grp"

"i2c": "i2c_grp"

"mdio": "mdio_grp"

"pwm": "pwm0_grp", "pwm1_grp", "pwm2_grp", "pwm3_grp"

"gpio_b": "gpio_b_0_grp", "gpio_b_1_grp", "gpio_b_2_grp", "gpio_b_3_grp"

"uart1": "uart1_grp"

"uart2": "uart2_grp"

"synce": "synce_grp"

"sata_led_grps": "sata0_led_grp", "sata1_led_grp"

"xtal_out": "xtal_out_grp"

"sdio": "sdio_pwr_grp", "sdio_1p8v_grp"

"switch_led": "switch_p05_led0_grp", "switch_p05_led1_grp"

"nand": "nand_grp"

"emmc": "emmc_grp"

* Oxford Semiconductor OXNAS SoC Family Pin Controller

Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and

../interrupt-controller/interrupts.txt for generic information regarding

pin controller, GPIO, and interrupt bindings.

OXNAS 'pin configuration node' is a node of a group of pins which can be

used for a specific device or function. This node represents configurations of

pins, optional function, and optional mux related configuration.

Required properties for pin controller node:

 - compatible: "oxsemi,ox810se-pinctrl"

 - oxsemi,sys-ctrl: a phandle to the system controller syscon node

Required properties for pin configuration sub-nodes:

 - pins: List of pins to which the configuration applies.

Optional properties for pin configuration sub-nodes:

----------------------------------------------------

 - function: Mux function for the specified pins.

 - bias-pull-up: Enable weak pull-up.

Example:

pinctrl: pinctrl {

	compatible = "oxsemi,ox810se-pinctrl";

	/* Regmap for sys registers */

	oxsemi,sys-ctrl = <&sys>;

	pinctrl_uart2: pinctrl_uart2 {

		uart2a {

			pins = "gpio31";

			function = "fct3";

		};

		uart2b {

			pins = "gpio32";

			function = "fct3";

		};

	};

};

uart2: serial@900000 {

	compatible = "ns16550a";

	reg = <0x900000 0x100000>;

	clocks = <&sysclk>;

	interrupts = <29>;

	reg-shift = <0>;

	fifo-size = <16>;

	reg-io-width = <1>;

	current-speed = <115200>;

	no-loopback-test;

	status = "disabled";

	resets = <&reset 22>;

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_uart2>;

};

Pincontrol driver for MAX77620 Power management IC from Maxim Semiconductor.

Device has 8 GPIO pins which can be configured as GPIO as well as the

special IO functions.

Please refer file <devicetree/bindings/pinctrl/pinctrl-bindings.txt>

for details of the common pinctrl bindings used by client devices,

including the meaning of the phrase "pin configuration node".

Optional Pinmux properties:

--------------------------

Following properties are required if default setting of pins are required

at boot.

- pinctrl-names: A pinctrl state named per <pinctrl-binding.txt>.

- pinctrl[0...n]: Properties to contain the phandle for pinctrl states per

		<pinctrl-binding.txt>.

The pin configurations are defined as child of the pinctrl states node. Each

sub-node have following properties:

Required properties:

------------------

- pins: List of pins. Valid values of pins properties are:

		      gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7.

Optional properties:

-------------------

Following are optional properties defined as pinmux DT binding document

<pinctrl-bindings.txt>. Absence of properties will leave the configuration

on default.

	function,

	drive-push-pull,

	drive-open-drain,

	bias-pull-up,

	bias-pull-down.

Valid values for function properties are:

	gpio, lpm-control-in, fps-out, 32k-out, sd0-dvs-in, sd1-dvs-in,

	reference-out

Theres is also customised properties for the GPIO1, GPIO2 and GPIO3. These

customised properties are required to configure FPS configuration parameters

of these GPIOs. Please refer <devicetree/bindings/mfd/max77620.txt> for more

detail of Flexible Power Sequence (FPS).

- maxim,active-fps-source:		FPS source for the GPIOs to get

					enabled/disabled when system is in

					active state.  Valid values are:

					- MAX77620_FPS_SRC_0,

						FPS source is FPS0.

					- MAX77620_FPS_SRC_1,

						FPS source is FPS1

					- MAX77620_FPS_SRC_2 and

						FPS source is FPS2

					- MAX77620_FPS_SRC_NONE.

						GPIO is not controlled

						by FPS events and it gets

						enabled/disabled by register

						access.

					Absence of this property will leave

					the FPS configuration register for that

					GPIO to default configuration.

- maxim,active-fps-power-up-slot:	Sequencing event slot number on which

					the GPIO get enabled when

					master FPS input event set to HIGH.

					Valid values are 0 to 7.

					This is applicable if FPS source is

					selected as FPS0, FPS1 or FPS2.

- maxim,active-fps-power-down-slot:	Sequencing event slot number on which

					the GPIO get disabled when master

					FPS input event set to LOW.

					Valid values are 0 to 7.

					This is applicable if FPS source is

					selected as FPS0, FPS1 or FPS2.

- maxim,suspend-fps-source:		This is same as property

					"maxim,active-fps-source" but value

					get configured when system enters in

					to suspend state.

- maxim,suspend-fps-power-up-slot:	This is same as property

					"maxim,active-fps-power-up-slot" but

					this value get configured into FPS

					configuration register when system

					enters into suspend.

					This is applicable if suspend state

					FPS source is selected as FPS0, FPS1 or

- maxim,suspend-fps-power-down-slot:	This is same as property

					"maxim,active-fps-power-down-slot" but

					this value get configured into FPS

					configuration register when system

					enters into suspend.

					This is applicable if suspend state

					FPS source is selected as FPS0, FPS1 or

					FPS2.

Example:

--------

#include <dt-bindings/mfd/max77620.h>

...

max77620@3c {

	pinctrl-names = "default";

	pinctrl-0 = <&spmic_default>;

	spmic_default: pinmux@0 {

		pin_gpio0 {

			pins = "gpio0";

			function = "gpio";

		};

		pin_gpio1 {

			pins = "gpio1";

			function = "fps-out";

			maxim,active-fps-source = <MAX77620_FPS_SRC_0>;

		};

		pin_gpio2 {

			pins = "gpio2";

			function = "fps-out";

			maxim,active-fps-source = <MAX77620_FPS_SRC_1>;

		};

	};

};