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Commit d8a507e6 authored by Jorik Jonker's avatar Jorik Jonker Committed by Maxime Ripard
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dts: sun8i-h3: add I2C0-2 peripherals to H3 SOC 



These peripherals can only be muxed to these pins, so they are
associated in the DTSI instead of the board files. This makes it very
easy to enable them using overlays or u-boot commands:

 => fdt set /soc/i2c@01c2ac00 status okay

Signed-off-by: default avatarJorik Jonker <jorik@kippendief.biz>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent 85e6f7ff

arch/arm/boot/dts/sun8i-h3.dtsi

+39 −0
Original line number Diff line number Diff line
@@ -491,6 +491,45 @@ 
			status = "disabled";

		};



		i2c0: i2c@01c2ac00 {

			compatible = "allwinner,sun6i-a31-i2c";

			reg = <0x01c2ac00 0x400>;

			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&ccu CLK_BUS_I2C0>;

			resets = <&ccu RST_BUS_I2C0>;

			pinctrl-names = "default";

			pinctrl-0 = <&i2c0_pins>;

			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

		};



		i2c1: i2c@01c2b000 {

			compatible = "allwinner,sun6i-a31-i2c";

			reg = <0x01c2b000 0x400>;

			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&ccu CLK_BUS_I2C1>;

			resets = <&ccu RST_BUS_I2C1>;

			pinctrl-names = "default";

			pinctrl-0 = <&i2c1_pins>;

			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

		};



		i2c2: i2c@01c2b400 {

			compatible = "allwinner,sun6i-a31-i2c";

			reg = <0x01c2b000 0x400>;

			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&ccu CLK_BUS_I2C2>;

			resets = <&ccu RST_BUS_I2C2>;

			pinctrl-names = "default";

			pinctrl-0 = <&i2c2_pins>;

			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

		};



		gic: interrupt-controller@01c81000 {

			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";

			reg = <0x01c81000 0x1000>,