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Commit d86f0b96 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "msm: kgsl: Add correct virtual address for GMEM"

parents 5400acce 592c5f76

drivers/gpu/msm/adreno.c

+5 −2
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2002,2007-2018, The Linux Foundation. All rights reserved.

 * Copyright (c) 2002,2007-2019, The Linux Foundation. All rights reserved.

 */

#include <linux/module.h>

#include <linux/uaccess.h>
@@ -2377,7 +2377,10 @@ static int adreno_prop_uche_gmem_addr(struct kgsl_device *device, 
	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	u64 vaddr;



	vaddr = (ADRENO_GPUREV(adreno_dev) >= 500) ? ADRENO_UCHE_GMEM_BASE : 0;

	if (ADRENO_GPUREV(adreno_dev) >= 500 && !(adreno_is_a650(adreno_dev)))

		vaddr = ADRENO_UCHE_GMEM_BASE;

	else

		vaddr = 0;



	return copy_prop(value, count, &vaddr, sizeof(vaddr));

}

drivers/gpu/msm/adreno_a6xx.c

+15 −8
Original line number Diff line number Diff line
@@ -875,7 +875,13 @@ static void a6xx_start(struct adreno_device *adreno_dev) 
	kgsl_regwrite(device, A6XX_UCHE_WRITE_THRU_BASE_LO, 0xfffff000);

	kgsl_regwrite(device, A6XX_UCHE_WRITE_THRU_BASE_HI, 0x0001ffff);



	/* Program the GMEM VA range for the UCHE path */

	/*

	 * Program the GMEM VA range for the UCHE path.

	 * From Kona onwards the GMEM VA address is 0, and

	 * UCHE_GMEM_RANGE registers are no longer used, so we don't

	 * have to program them.

	 */

	if (!adreno_is_a650(adreno_dev)) {

		kgsl_regwrite(device, A6XX_UCHE_GMEM_RANGE_MIN_LO,

					ADRENO_UCHE_GMEM_BASE);

		kgsl_regwrite(device, A6XX_UCHE_GMEM_RANGE_MIN_HI, 0x0);
@@ -883,6 +889,7 @@ static void a6xx_start(struct adreno_device *adreno_dev) 
					ADRENO_UCHE_GMEM_BASE +

					adreno_dev->gmem_size - 1);

		kgsl_regwrite(device, A6XX_UCHE_GMEM_RANGE_MAX_HI, 0x0);

	}



	kgsl_regwrite(device, A6XX_UCHE_FILTER_CNTL, 0x804);

	kgsl_regwrite(device, A6XX_UCHE_CACHE_WAYS, 0x4);