Commit d86d46af authored Dec 01, 2016 by Boris Brezillon Committed by Stephen Boyd Dec 08, 2016

clk: bcm: Allow rate change propagation to PLLH_AUX on VEC clock



The VEC clock requires needs to be set at exactly 108MHz. Allow rate
change propagation on PLLH_AUX to match this requirement wihtout
impacting other IPs (PLLH is currently only used by the HDMI encoder,
which cannot be enabled when the VEC encoder is enabled).

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

parent 155e8b3b

drivers/clk/bcm/clk-bcm2835.c

+6 −1

Original line number	Diff line number	Diff line
		@@ -1861,7 +1861,12 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
		.ctl_reg = CM_VECCTL,
		.div_reg = CM_VECDIV,
		.int_bits = 4,
		.frac_bits = 0),
		.frac_bits = 0,
		/*
		* Allow rate change propagation only on PLLH_AUX which is
		* assigned index 7 in the parent array.
		*/
		.set_rate_parent = BIT(7)),

		/* dsi clocks */
		[BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK(