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Commit d7ea335c authored by Steven J. Hill's avatar Steven J. Hill Committed by Ralf Baechle
Browse files

MIPS: Remove usage of CSRC_R4K_LIB config option.



Manuel Lauss <manuel.lauss@gmail.com> writes:

I introduced it as a fallback because early revisions of Alchemy hardware
we shipped had a non-functional 32kHz timer and had to rely on the r4k
timer instead.  Previously the r4k timer was initialized regardless, but
it's useless with the "wait" instruction.

So long story short:   I need either the on-chip 32kHz timer OR the r4k
timer if the 32kHz one is unusable, but not both, and r4k timer is useless
when au1k_idle is in use.

The current in-kernel Alchemy boards all work with the 32kHz timer, so I'm
not against removing R4K_LIB symbols.

Signed-off-by: default avatarSteven J. Hill <sjhill@mips.com>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent dcb96a4e
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+1 −5
Original line number Diff line number Diff line
@@ -55,7 +55,7 @@ config MIPS_ALCHEMY
	bool "Alchemy processor based machines"
	select 64BIT_PHYS_ADDR
	select CEVT_R4K_LIB
	select CSRC_R4K_LIB
	select CSRC_R4K
	select IRQ_CPU
	select SYS_HAS_CPU_MIPS32_R1
	select SYS_SUPPORTS_32BIT_KERNEL
@@ -948,11 +948,7 @@ config CSRC_IOASIC
config CSRC_POWERTV
	bool

config CSRC_R4K_LIB
	bool

config CSRC_R4K
	select CSRC_R4K_LIB
	bool

config CSRC_SB1250
+1 −1
Original line number Diff line number Diff line
@@ -71,7 +71,7 @@ static inline int mips_clockevent_init(void)
/*
 * Initialize the count register as a clocksource
 */
#ifdef CONFIG_CSRC_R4K_LIB
#ifdef CONFIG_CSRC_R4K
extern int init_r4k_clocksource(void);
#endif

+1 −1
Original line number Diff line number Diff line
@@ -25,7 +25,7 @@ obj-$(CONFIG_CEVT_TXX9) += cevt-txx9.o
obj-$(CONFIG_CSRC_BCM1480)	+= csrc-bcm1480.o
obj-$(CONFIG_CSRC_IOASIC)	+= csrc-ioasic.o
obj-$(CONFIG_CSRC_POWERTV)	+= csrc-powertv.o
obj-$(CONFIG_CSRC_R4K_LIB)	+= csrc-r4k.o
obj-$(CONFIG_CSRC_R4K)		+= csrc-r4k.o
obj-$(CONFIG_CSRC_SB1250)	+= csrc-sb1250.o
obj-$(CONFIG_SYNC_R4K)		+= sync-r4k.o