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Commit d7dce6a3 authored by Kiran AVND's avatar Kiran AVND Committed by Mauro Carvalho Chehab
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[media] s5p-mfc: keep RISC ON during reset for V7/V8 



Reset sequence for MFC V7 and V8 do not need RISC_ON
to be set to 0, while for MFC V6 it is still needed.

Also, remove a couple of register settings during Reset
which are not needed from V6 onwards.

Signed-off-by: default avatarKiran AVND <avnd.kiran@samsung.com>
Signed-off-by: default avatarArun Kumar K <arun.kk@samsung.com>
Signed-off-by: default avatarKamil Debski <k.debski@samsung.com>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@osg.samsung.com>
parent bb21c54a

drivers/media/platform/s5p-mfc/s5p_mfc_common.h

+1 −0
Original line number Diff line number Diff line
@@ -340,6 +340,7 @@ struct s5p_mfc_dev { 
	struct s5p_mfc_hw_cmds *mfc_cmds;

	const struct s5p_mfc_regs *mfc_regs;

	enum s5p_mfc_fw_ver fw_ver;

	bool risc_on; /* indicates if RISC is on or off */

};



/**

drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c

+15 −10
Original line number Diff line number Diff line
@@ -139,12 +139,6 @@ int s5p_mfc_reset(struct s5p_mfc_dev *dev) 
	mfc_debug_enter();



	if (IS_MFCV6_PLUS(dev)) {

		/* Reset IP */

		/*  except RISC, reset */

		mfc_write(dev, 0xFEE, S5P_FIMV_MFC_RESET_V6);

		/*  reset release */

		mfc_write(dev, 0x0, S5P_FIMV_MFC_RESET_V6);



		/* Zero Initialization of MFC registers */

		mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD_V6);

		mfc_write(dev, 0, S5P_FIMV_HOST2RISC_CMD_V6);
@@ -153,8 +147,13 @@ int s5p_mfc_reset(struct s5p_mfc_dev *dev) 
		for (i = 0; i < S5P_FIMV_REG_CLEAR_COUNT_V6; i++)

			mfc_write(dev, 0, S5P_FIMV_REG_CLEAR_BEGIN_V6 + (i*4));



		/* Reset */

		/* Reset

		 * set RISC_ON to 0 during power_on & wake_up.

		 * V6 needs RISC_ON set to 0 during reset also.

		 */

		if ((!dev->risc_on) || (!IS_MFCV7(dev)))

			mfc_write(dev, 0, S5P_FIMV_RISC_ON_V6);



		mfc_write(dev, 0x1FFF, S5P_FIMV_MFC_RESET_V6);

		mfc_write(dev, 0, S5P_FIMV_MFC_RESET_V6);

	} else {
@@ -226,6 +225,7 @@ int s5p_mfc_init_hw(struct s5p_mfc_dev *dev) 
	/* 0. MFC reset */

	mfc_debug(2, "MFC reset..\n");

	s5p_mfc_clock_on();

	dev->risc_on = 0;

	ret = s5p_mfc_reset(dev);

	if (ret) {

		mfc_err("Failed to reset MFC - timeout\n");
@@ -238,8 +238,10 @@ int s5p_mfc_init_hw(struct s5p_mfc_dev *dev) 
	s5p_mfc_clear_cmds(dev);

	/* 3. Release reset signal to the RISC */

	s5p_mfc_clean_dev_int_flags(dev);

	if (IS_MFCV6_PLUS(dev))

	if (IS_MFCV6_PLUS(dev)) {

		dev->risc_on = 1;

		mfc_write(dev, 0x1, S5P_FIMV_RISC_ON_V6);

	}

	else

		mfc_write(dev, 0x3ff, S5P_FIMV_SW_RESET);

	mfc_debug(2, "Will now wait for completion of firmware transfer\n");
@@ -336,6 +338,7 @@ int s5p_mfc_wakeup(struct s5p_mfc_dev *dev) 
	/* 0. MFC reset */

	mfc_debug(2, "MFC reset..\n");

	s5p_mfc_clock_on();

	dev->risc_on = 0;

	ret = s5p_mfc_reset(dev);

	if (ret) {

		mfc_err("Failed to reset MFC - timeout\n");
@@ -354,8 +357,10 @@ int s5p_mfc_wakeup(struct s5p_mfc_dev *dev) 
		return ret;

	}

	/* 4. Release reset signal to the RISC */

	if (IS_MFCV6_PLUS(dev))

	if (IS_MFCV6_PLUS(dev)) {

		dev->risc_on = 1;

		mfc_write(dev, 0x1, S5P_FIMV_RISC_ON_V6);

	}

	else

		mfc_write(dev, 0x3ff, S5P_FIMV_SW_RESET);

	mfc_debug(2, "Ok, now will write a command to wakeup the system\n");