Loading drivers/clk/qcom/dispcc-bengal.c +6 −5 Original line number Diff line number Diff line Loading @@ -70,6 +70,11 @@ static const char * const disp_cc_parent_names_2[] = { "core_bi_pll_test_se", }; static const char * const disp_cc_parent_names_2_ao[] = { "bi_tcxo_ao", "core_bi_pll_test_se", }; static const struct parent_map disp_cc_parent_map_3[] = { { P_BI_TCXO, 0 }, { P_GPLL0_OUT_MAIN, 4 }, Loading Loading @@ -387,13 +392,9 @@ static struct clk_rcg2 disp_cc_xo_clk_src = { .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_xo_clk_src", .parent_names = disp_cc_parent_names_2, .parent_names = disp_cc_parent_names_2_ao, .num_parents = 2, .ops = &clk_rcg2_ops, .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_MIN] = 19200000}, }, }; Loading Loading
drivers/clk/qcom/dispcc-bengal.c +6 −5 Original line number Diff line number Diff line Loading @@ -70,6 +70,11 @@ static const char * const disp_cc_parent_names_2[] = { "core_bi_pll_test_se", }; static const char * const disp_cc_parent_names_2_ao[] = { "bi_tcxo_ao", "core_bi_pll_test_se", }; static const struct parent_map disp_cc_parent_map_3[] = { { P_BI_TCXO, 0 }, { P_GPLL0_OUT_MAIN, 4 }, Loading Loading @@ -387,13 +392,9 @@ static struct clk_rcg2 disp_cc_xo_clk_src = { .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_xo_clk_src", .parent_names = disp_cc_parent_names_2, .parent_names = disp_cc_parent_names_2_ao, .num_parents = 2, .ops = &clk_rcg2_ops, .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_MIN] = 19200000}, }, }; Loading