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Commit d6ec9d9a authored by Linus Torvalds's avatar Linus Torvalds
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Merge branch 'x86-asm-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 core updates from Ingo Molnar:
 "Note that in this cycle most of the x86 topics interacted at a level
  that caused them to be merged into tip:x86/asm - but this should be a
  temporary phenomenon, hopefully we'll back to the usual patterns in
  the next merge window.

  The main changes in this cycle were:

  Hardware enablement:

   - Add support for the Intel UMIP (User Mode Instruction Prevention)
     CPU feature. This is a security feature that disables certain
     instructions such as SGDT, SLDT, SIDT, SMSW and STR. (Ricardo Neri)

     [ Note that this is disabled by default for now, there are some
       smaller enhancements in the pipeline that I'll follow up with in
       the next 1-2 days, which allows this to be enabled by default.]

   - Add support for the AMD SEV (Secure Encrypted Virtualization) CPU
     feature, on top of SME (Secure Memory Encryption) support that was
     added in v4.14. (Tom Lendacky, Brijesh Singh)

   - Enable new SSE/AVX/AVX512 CPU features: AVX512_VBMI2, GFNI, VAES,
     VPCLMULQDQ, AVX512_VNNI, AVX512_BITALG. (Gayatri Kammela)

  Other changes:

   - A big series of entry code simplifications and enhancements (Andy
     Lutomirski)

   - Make the ORC unwinder default on x86 and various objtool
     enhancements. (Josh Poimboeuf)

   - 5-level paging enhancements (Kirill A. Shutemov)

   - Micro-optimize the entry code a bit (Borislav Petkov)

   - Improve the handling of interdependent CPU features in the early
     FPU init code (Andi Kleen)

   - Build system enhancements (Changbin Du, Masahiro Yamada)

   - ... plus misc enhancements, fixes and cleanups"

* 'x86-asm-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (118 commits)
  x86/build: Make the boot image generation less verbose
  selftests/x86: Add tests for the STR and SLDT instructions
  selftests/x86: Add tests for User-Mode Instruction Prevention
  x86/traps: Fix up general protection faults caused by UMIP
  x86/umip: Enable User-Mode Instruction Prevention at runtime
  x86/umip: Force a page fault when unable to copy emulated result to user
  x86/umip: Add emulation code for UMIP instructions
  x86/cpufeature: Add User-Mode Instruction Prevention definitions
  x86/insn-eval: Add support to resolve 16-bit address encodings
  x86/insn-eval: Handle 32-bit address encodings in virtual-8086 mode
  x86/insn-eval: Add wrapper function for 32 and 64-bit addresses
  x86/insn-eval: Add support to resolve 32-bit address encodings
  x86/insn-eval: Compute linear address in several utility functions
  resource: Fix resource_size.cocci warnings
  X86/KVM: Clear encryption attribute when SEV is active
  X86/KVM: Decrypt shared per-cpu variables when SEV is active
  percpu: Introduce DEFINE_PER_CPU_DECRYPTED
  x86: Add support for changing memory encryption attribute in early boot
  x86/io: Unroll string I/O when SEV is active
  x86/boot: Add early boot support when running with SEV active
  ...
parents 3e201463 91a6a6cf

Documentation/x86/amd-memory-encryption.txt

+26 −4
Original line number Diff line number Diff line 
Secure Memory Encryption (SME) is a feature found on AMD processors.

Secure Memory Encryption (SME) and Secure Encrypted Virtualization (SEV) are

features found on AMD processors.



SME provides the ability to mark individual pages of memory as encrypted using

the standard x86 page tables.  A page that is marked encrypted will be
@@ -6,24 +7,38 @@ automatically decrypted when read from DRAM and encrypted when written to 
DRAM.  SME can therefore be used to protect the contents of DRAM from physical

attacks on the system.



SEV enables running encrypted virtual machines (VMs) in which the code and data

of the guest VM are secured so that a decrypted version is available only

within the VM itself. SEV guest VMs have the concept of private and shared

memory. Private memory is encrypted with the guest-specific key, while shared

memory may be encrypted with hypervisor key. When SME is enabled, the hypervisor

key is the same key which is used in SME.



A page is encrypted when a page table entry has the encryption bit set (see

below on how to determine its position).  The encryption bit can also be

specified in the cr3 register, allowing the PGD table to be encrypted. Each

successive level of page tables can also be encrypted by setting the encryption

bit in the page table entry that points to the next table. This allows the full

page table hierarchy to be encrypted. Note, this means that just because the

encryption bit is set in cr3, doesn't imply the full hierarchy is encyrpted.

encryption bit is set in cr3, doesn't imply the full hierarchy is encrypted.

Each page table entry in the hierarchy needs to have the encryption bit set to

achieve that. So, theoretically, you could have the encryption bit set in cr3

so that the PGD is encrypted, but not set the encryption bit in the PGD entry

for a PUD which results in the PUD pointed to by that entry to not be

encrypted.



Support for SME can be determined through the CPUID instruction. The CPUID

function 0x8000001f reports information related to SME:

When SEV is enabled, instruction pages and guest page tables are always treated

as private. All the DMA operations inside the guest must be performed on shared

memory. Since the memory encryption bit is controlled by the guest OS when it

is operating in 64-bit or 32-bit PAE mode, in all other modes the SEV hardware

forces the memory encryption bit to 1.



Support for SME and SEV can be determined through the CPUID instruction. The

CPUID function 0x8000001f reports information related to SME:



	0x8000001f[eax]:

		Bit[0] indicates support for SME

		Bit[1] indicates support for SEV

	0x8000001f[ebx]:

		Bits[5:0]  pagetable bit number used to activate memory

			   encryption
@@ -39,6 +54,13 @@ determine if SME is enabled and/or to enable memory encryption: 
		Bit[23]   0 = memory encryption features are disabled

			  1 = memory encryption features are enabled



If SEV is supported, MSR 0xc0010131 (MSR_AMD64_SEV) can be used to determine if

SEV is active:



	0xc0010131:

		Bit[0]	  0 = memory encryption is not active

			  1 = memory encryption is active



Linux relies on BIOS to set this bit if BIOS has determined that the reduction

in the physical address space as a result of enabling memory encryption (see

CPUID information above) will not conflict with the address space resource

Documentation/x86/orc-unwinder.txt

+1 −1
Original line number Diff line number Diff line
@@ -4,7 +4,7 @@ ORC unwinder 
Overview

--------



The kernel CONFIG_ORC_UNWINDER option enables the ORC unwinder, which is

The kernel CONFIG_UNWINDER_ORC option enables the ORC unwinder, which is

similar in concept to a DWARF unwinder.  The difference is that the

format of the ORC data is much simpler than DWARF, which in turn allows

the ORC unwinder to be much simpler and faster.

Documentation/x86/x86_64/mm.txt

+1 −1
Original line number Diff line number Diff line
@@ -34,7 +34,7 @@ ff92000000000000 - ffd1ffffffffffff (=54 bits) vmalloc/ioremap space 
ffd2000000000000 - ffd3ffffffffffff (=49 bits) hole

ffd4000000000000 - ffd5ffffffffffff (=49 bits) virtual memory map (512TB)

... unused hole ...

ffd8000000000000 - fff7ffffffffffff (=53 bits) kasan shadow memory (8PB)

ffdf000000000000 - fffffc0000000000 (=53 bits) kasan shadow memory (8PB)

... unused hole ...

ffffff0000000000 - ffffff7fffffffff (=39 bits) %esp fixup stacks

... unused hole ...

Makefile

+2 −2
Original line number Diff line number Diff line
@@ -934,8 +934,8 @@ ifdef CONFIG_STACK_VALIDATION 
  ifeq ($(has_libelf),1)

    objtool_target := tools/objtool FORCE

  else

    ifdef CONFIG_ORC_UNWINDER

      $(error "Cannot generate ORC metadata for CONFIG_ORC_UNWINDER=y, please install libelf-dev, libelf-devel or elfutils-libelf-devel")

    ifdef CONFIG_UNWINDER_ORC

      $(error "Cannot generate ORC metadata for CONFIG_UNWINDER_ORC=y, please install libelf-dev, libelf-devel or elfutils-libelf-devel")

    else

      $(warning "Cannot use CONFIG_STACK_VALIDATION=y, please install libelf-dev, libelf-devel or elfutils-libelf-devel")

    endif

arch/powerpc/kernel/machine_kexec_file_64.c

+9 −3
Original line number Diff line number Diff line
@@ -91,11 +91,13 @@ int arch_kimage_file_post_load_cleanup(struct kimage *image) 
 * and that value will be returned. If all free regions are visited without

 * func returning non-zero, then zero will be returned.

 */

int arch_kexec_walk_mem(struct kexec_buf *kbuf, int (*func)(u64, u64, void *))

int arch_kexec_walk_mem(struct kexec_buf *kbuf,

			int (*func)(struct resource *, void *))

{

	int ret = 0;

	u64 i;

	phys_addr_t mstart, mend;

	struct resource res = { };



	if (kbuf->top_down) {

		for_each_free_mem_range_reverse(i, NUMA_NO_NODE, 0,
@@ -105,7 +107,9 @@ int arch_kexec_walk_mem(struct kexec_buf *kbuf, int (*func)(u64, u64, void *)) 
			 * range while in kexec, end points to the last byte

			 * in the range.

			 */

			ret = func(mstart, mend - 1, kbuf);

			res.start = mstart;

			res.end = mend - 1;

			ret = func(&res, kbuf);

			if (ret)

				break;

		}
@@ -117,7 +121,9 @@ int arch_kexec_walk_mem(struct kexec_buf *kbuf, int (*func)(u64, u64, void *)) 
			 * range while in kexec, end points to the last byte

			 * in the range.

			 */

			ret = func(mstart, mend - 1, kbuf);

			res.start = mstart;

			res.end = mend - 1;

			ret = func(&res, kbuf);

			if (ret)

				break;

		}