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Commit d6a32c84 authored by Hemant Kumar's avatar Hemant Kumar
Browse files

usb: phy: Do not perform phy reset if EUD is enabled



If EUD is enabled and phy reset is performed due to
spoof connect, EUD enumeration fails. Fix this issue
by reading EUD enable register before phy init. Check
the status in and msm_hsphy_dpdm_regulator_enable()
which also performs phy reset.

Change-Id: I8f473c4e50611e1f444719ee498e3e49ae82cbe1
Signed-off-by: default avatarHemant Kumar <hemantk@codeaurora.org>
parent c4e39324
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+23 −0
Original line number Original line Diff line number Diff line
@@ -71,6 +71,7 @@
struct msm_hsphy {
struct msm_hsphy {
	struct usb_phy		phy;
	struct usb_phy		phy;
	void __iomem		*base;
	void __iomem		*base;
	void __iomem		*eud_enable_reg;


	struct clk		*ref_clk_src;
	struct clk		*ref_clk_src;
	struct clk		*cfg_ahb_clk;
	struct clk		*cfg_ahb_clk;
@@ -319,11 +320,17 @@ static int msm_hsphy_init(struct usb_phy *uphy)


	dev_dbg(uphy->dev, "%s\n", __func__);
	dev_dbg(uphy->dev, "%s\n", __func__);


	if (phy->eud_enable_reg && readl_relaxed(phy->eud_enable_reg)) {
		dev_err(phy->phy.dev, "eud is enabled\n");
		return 0;
	}

	ret = msm_hsphy_enable_power(phy, true);
	ret = msm_hsphy_enable_power(phy, true);
	if (ret)
	if (ret)
		return ret;
		return ret;


	msm_hsphy_enable_clocks(phy, true);
	msm_hsphy_enable_clocks(phy, true);

	msm_hsphy_reset(phy);
	msm_hsphy_reset(phy);


	msm_usb_write_readback(phy->base, USB2_PHY_USB_PHY_CFG0,
	msm_usb_write_readback(phy->base, USB2_PHY_USB_PHY_CFG0,
@@ -461,6 +468,11 @@ static int msm_hsphy_dpdm_regulator_enable(struct regulator_dev *rdev)
	dev_dbg(phy->phy.dev, "%s dpdm_enable:%d\n",
	dev_dbg(phy->phy.dev, "%s dpdm_enable:%d\n",
				__func__, phy->dpdm_enable);
				__func__, phy->dpdm_enable);


	if (phy->eud_enable_reg && readl_relaxed(phy->eud_enable_reg)) {
		dev_err(phy->phy.dev, "eud is enabled\n");
		return 0;
	}

	mutex_lock(&phy->phy_lock);
	mutex_lock(&phy->phy_lock);
	if (!phy->dpdm_enable) {
	if (!phy->dpdm_enable) {
		ret = msm_hsphy_enable_power(phy, true);
		ret = msm_hsphy_enable_power(phy, true);
@@ -470,6 +482,7 @@ static int msm_hsphy_dpdm_regulator_enable(struct regulator_dev *rdev)
		}
		}


		msm_hsphy_enable_clocks(phy, true);
		msm_hsphy_enable_clocks(phy, true);

		msm_hsphy_reset(phy);
		msm_hsphy_reset(phy);


		/*
		/*
@@ -608,6 +621,16 @@ static int msm_hsphy_probe(struct platform_device *pdev)
				phy->phy_rcal_reg);
				phy->phy_rcal_reg);
	}
	}


	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
			"eud_enable_reg");
	if (res) {
		phy->eud_enable_reg = devm_ioremap_resource(dev, res);
		if (IS_ERR(phy->eud_enable_reg)) {
			dev_err(dev, "err getting eud_enable_reg address\n");
			return PTR_ERR(phy->eud_enable_reg);
		}
	}

	/* ref_clk_src is needed irrespective of SE_CLK or DIFF_CLK usage */
	/* ref_clk_src is needed irrespective of SE_CLK or DIFF_CLK usage */
	phy->ref_clk_src = devm_clk_get(dev, "ref_clk_src");
	phy->ref_clk_src = devm_clk_get(dev, "ref_clk_src");
	if (IS_ERR(phy->ref_clk_src)) {
	if (IS_ERR(phy->ref_clk_src)) {