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Commit d5de797f authored by Ken Wang's avatar Ken Wang Committed by Alex Deucher
Browse files

drm/amdgpu: fix vega10 graphic hang issue in S3 test 



mmVGT_INDEX_TYPE has no default value, need to make sure
it's initialized when gfx is initialized.

Signed-off-by: default avatarKen Wang <Ken.Wang@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 33476319

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+8 −2
Original line number Diff line number Diff line
@@ -2157,7 +2157,7 @@ static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev) 
	struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];

	const struct cs_section_def *sect = NULL;

	const struct cs_extent_def *ext = NULL;

	int r, i;

	int r, i, tmp;



	/* init the CP */

	WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
@@ -2165,7 +2165,7 @@ static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev) 


	gfx_v9_0_cp_gfx_enable(adev, true);



	r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4);

	r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3);

	if (r) {

		DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);

		return r;
@@ -2203,6 +2203,12 @@ static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev) 
	amdgpu_ring_write(ring, 0x8000);

	amdgpu_ring_write(ring, 0x8000);



	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG,1));

	tmp = (PACKET3_SET_UCONFIG_REG_INDEX_TYPE |

		(SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START));

	amdgpu_ring_write(ring, tmp);

	amdgpu_ring_write(ring, 0);



	amdgpu_ring_commit(ring);



	return 0;

drivers/gpu/drm/amd/amdgpu/soc15d.h

+1 −0
Original line number Diff line number Diff line
@@ -250,6 +250,7 @@ 
#define	PACKET3_SET_UCONFIG_REG				0x79

#define		PACKET3_SET_UCONFIG_REG_START			0x0000c000

#define		PACKET3_SET_UCONFIG_REG_END			0x0000c400

#define		PACKET3_SET_UCONFIG_REG_INDEX_TYPE		(2 << 28)

#define	PACKET3_SCRATCH_RAM_WRITE			0x7D

#define	PACKET3_SCRATCH_RAM_READ			0x7E

#define	PACKET3_LOAD_CONST_RAM				0x80