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Commit d59dbedc authored by Vivek Aknurwar's avatar Vivek Aknurwar Committed by Gerrit - the friendly Code Review server
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dt-bindings: clock: Add gpu cc driver bindings for KONA 



Add binding documentation for device tree examples headers
to help describe kona gpu cc driver.

Change-Id: I186c19c7eb591123804e699081955d9e67431338
Signed-off-by: default avatarVivek Aknurwar <viveka@codeaurora.org>
parent 86452c09

Documentation/devicetree/bindings/clock/qcom,gpucc.txt

0 → 100644
+29 −0
Original line number Diff line number Diff line 
Qualcomm Technologies, Inc. Graphics Clock & Reset Controller Binding

--------------------------------------------------------------------



Required properties :

- compatible: shall contain one of the following:

		"qcom,gpucc-kona".

- reg: shall contain base register offset and size.

- reg-names: names of registers listed in the same order as in the reg property.

		Must contain "cc_base".

- #clock-cells: from common clock binding, shall contain 1.

- #reset-cells: from common reset binding, shall contain 1.

- vdd_cx-supply: The vdd_cx logic rail supply.

- vdd_mx-supply: The vdd_mx logic rail supply.



Optional properties :

- #power-domain-cells : from generic power domain binding, shall contain 1.



Example:



	clock_gpucc: clock-controller@3d90000 {

		compatible = "qcom,gpucc-kona";

		reg = <0x3d90000 0x9000>;

		reg-names = "cc_base";

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		vdd_mx-supply = <&VDD_MX_LEVEL>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};

include/dt-bindings/clock/qcom,gpucc-kona.h

+9 −3
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */

/*

 * Copyright (c) 2018, The Linux Foundation. All rights reserved.

 */



#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_KONA_H

#define _DT_BINDINGS_CLK_QCOM_GPU_CC_KONA_H
@@ -19,6 +21,7 @@ 
#define GPU_CC_GX_QDSS_TSCTR_CLK				12

#define GPU_CC_GX_VSENSE_CLK					13

#define GPU_CC_PLL1						14

#define GPU_CC_SLEEP_CLK					15



#define CX_GDSC							0

#define GX_GDSC							1
@@ -28,7 +31,10 @@ 
#define GPUCC_GPU_CC_GFX3D_AON_BCR				2

#define GPUCC_GPU_CC_GMU_BCR					3

#define GPUCC_GPU_CC_GX_BCR					4

#define GPUCC_GPU_CC_SPDM_BCR					5

#define GPUCC_GPU_CC_XO_BCR					6

#define GPUCC_GPU_CC_XO_BCR					5



#define MEASURE_ONLY_GPU_CC_CX_GFX3D_CLK			0

#define MEASURE_ONLY_GPU_CC_CX_GFX3D_SLV_CLK			1

#define MEASURE_ONLY_GPU_CC_GX_GFX3D_CLK			2



#endif