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Commit d554b5e1 authored by Martin K. Petersen's avatar Martin K. Petersen Committed by Sagi Grimberg
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nvme: Quirks for PM1725 controllers 



PM1725 controllers have a couple of quirks that need to be handled in
the driver:

 - I/O queue depth must be limited to 64 entries on controllers that do
   not report MQES.

 - The host interface registers go offline briefly while resetting the
   chip. Thus a delay is needed before checking whether the controller
   is ready.

Note that the admin queue depth is also limited to 64 on older versions
of this board. Since our NVME_AQ_DEPTH is now 32 that is no longer an
issue.

Signed-off-by: default avatarMartin K. Petersen <martin.petersen@oracle.com>
Signed-off-by: default avatarSagi Grimberg <sagi@grimberg.me>
parent a84ebb83

drivers/nvme/host/pci.c

+10 −0
Original line number Diff line number Diff line
@@ -1908,6 +1908,12 @@ static int nvme_pci_enable(struct nvme_dev *dev) 
		dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "

			"set queue depth=%u to work around controller resets\n",

			dev->q_depth);

	} else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&

		   (pdev->device == 0xa821 || pdev->device == 0xa822) &&

		   NVME_CAP_MQES(cap) == 0) {

		dev->q_depth = 64;

		dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "

                        "set queue depth=%u\n", dev->q_depth);

	}



	/*
@@ -2454,6 +2460,10 @@ static const struct pci_device_id nvme_id_table[] = { 
		.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },

	{ PCI_DEVICE(0x1c5f, 0x0540),	/* Memblaze Pblaze4 adapter */

		.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },

	{ PCI_DEVICE(0x144d, 0xa821),   /* Samsung PM1725 */

		.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },

	{ PCI_DEVICE(0x144d, 0xa822),   /* Samsung PM1725a */

		.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },

	{ PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },

	{ PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },

	{ PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },