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Commit d53d7866 authored by Yue Hin Lau's avatar Yue Hin Lau Committed by Alex Deucher
Browse files

drm/amd/display: removing remaining register definitions work around 



Signed-off-by: default avatarYue Hin Lau <Yuehin.Lau@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 68d77dd8

drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h

+8 −8
Original line number Diff line number Diff line
@@ -179,16 +179,11 @@ 
	SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \

	SR(DCHUBBUB_TEST_DEBUG_INDEX), \

	SR(DCHUBBUB_TEST_DEBUG_DATA), \

	SR(DC_IP_REQUEST_CNTL), \

	SR(DIO_MEM_PWR_CTRL), \

	SR(DCCG_GATE_DISABLE_CNTL), \

	SR(DCCG_GATE_DISABLE_CNTL2), \

	SR(DCFCLK_CNTL),\

	SR(DCFCLK_CNTL), \

	SR(D1VGA_CONTROL), \

	SR(D2VGA_CONTROL), \

	SR(D3VGA_CONTROL), \

	SR(D4VGA_CONTROL), \

	/* todo:  get these from GVM instead of reading registers ourselves */\

	MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),\

	MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),\
@@ -228,7 +223,12 @@ 
	SR(DOMAIN4_PG_STATUS), \

	SR(DOMAIN5_PG_STATUS), \

	SR(DOMAIN6_PG_STATUS), \

	SR(DOMAIN7_PG_STATUS)

	SR(DOMAIN7_PG_STATUS), \

	SR(D1VGA_CONTROL), \

	SR(D2VGA_CONTROL), \

	SR(D3VGA_CONTROL), \

	SR(D4VGA_CONTROL), \

	SR(DC_IP_REQUEST_CNTL)



struct dce_hwseq_registers {

	uint32_t DCFE_CLOCK_CONTROL[6];
@@ -415,7 +415,6 @@ struct dce_hwseq_registers { 
	HWS_SF(DPP_TOP0_, DPP_CONTROL, DPP_CLOCK_ENABLE, mask_sh), \

	HWS_SF(OPP_PIPE0_, OPP_PIPE_CONTROL, OPP_PIPE_CLOCK_EN, mask_sh),\

	HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \

	HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \

	HWS_SF(, DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, mask_sh), \

	HWS_SF(, DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, mask_sh), \

	HWS_SF(, DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, mask_sh), \
@@ -467,7 +466,8 @@ struct dce_hwseq_registers { 
	HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \

	HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \

	HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \

	HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh)

	HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \

	HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh)



#define HWSEQ_REG_FIELD_LIST(type) \

	type DCFE_CLOCK_ENABLE; \

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h

+14 −7
Original line number Diff line number Diff line
@@ -44,8 +44,6 @@ 
	SRI(DC_HPD_CONTROL, HPD, id)



#define LE_COMMON_REG_LIST_BASE(id) \

	SR(LVTMA_PWRSEQ_CNTL), \

	SR(LVTMA_PWRSEQ_STATE), \

	SR(DMCU_RAM_ACCESS_CTRL), \

	SR(DMCU_IRAM_RD_CTRL), \

	SR(DMCU_IRAM_RD_DATA), \
@@ -71,6 +69,10 @@ 
	SRI(DP_DPHY_FAST_TRAINING, DP, id), \

	SRI(DP_SEC_CNTL1, DP, id)



#define LE_EDP_REG_LIST(id)\

	SR(LVTMA_PWRSEQ_CNTL), \

	SR(LVTMA_PWRSEQ_STATE)



#define LE_COMMON_REG_LIST(id)\

	LE_COMMON_REG_LIST_BASE(id), \

	SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
@@ -79,33 +81,38 @@ 


#define LE_DCE80_REG_LIST(id)\

	SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \

	LE_COMMON_REG_LIST_BASE(id)

	LE_COMMON_REG_LIST_BASE(id), \

	LE_EDP_REG_LIST(id)



#define LE_DCE100_REG_LIST(id)\

	LE_COMMON_REG_LIST_BASE(id), \

	SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \

	SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \

	SR(DCI_MEM_PWR_STATUS)

	SR(DCI_MEM_PWR_STATUS), \

	LE_EDP_REG_LIST(id)



#define LE_DCE110_REG_LIST(id)\

	LE_COMMON_REG_LIST_BASE(id), \

	SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \

	SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \

	SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id), \

	SR(DCI_MEM_PWR_STATUS)

	SR(DCI_MEM_PWR_STATUS), \

	LE_EDP_REG_LIST(id)



#define LE_DCE120_REG_LIST(id)\

	LE_COMMON_REG_LIST_BASE(id), \

	SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \

	SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id), \

	SR(DCI_MEM_PWR_STATUS)

	SR(DCI_MEM_PWR_STATUS), \

	LE_EDP_REG_LIST(id)



#define LE_DCN10_REG_LIST(id)\

	LE_COMMON_REG_LIST_BASE(id), \

	SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \

	SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \

	SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id), \

	SR(DMU_MEM_PWR_CNTL)

	SR(DMU_MEM_PWR_CNTL), \

	LE_EDP_REG_LIST(id)



struct dce110_link_enc_aux_registers {

	uint32_t AUX_CONTROL;

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h

+1 −10
Original line number Diff line number Diff line
@@ -71,11 +71,7 @@ 
	SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\

	SRI(OPPBUF_CONTROL, OPPBUF, inst),\

	SRI(OPPBUF_3D_PARAMETERS_0, OPPBUF, inst),\

	SRI(CONTROL, VTG, inst),\

	SR(D1VGA_CONTROL),\

	SR(D2VGA_CONTROL),\

	SR(D3VGA_CONTROL),\

	SR(D4VGA_CONTROL)

	SRI(CONTROL, VTG, inst)



#define TG_COMMON_REG_LIST_DCN1_0(inst) \

	TG_COMMON_REG_LIST_DCN(inst),\
@@ -128,11 +124,6 @@ struct dcn_tg_registers { 
	uint32_t OPPBUF_CONTROL;

	uint32_t OPPBUF_3D_PARAMETERS_0;

	uint32_t CONTROL;

	/*todo: move VGA to HWSS */

	uint32_t D1VGA_CONTROL;

	uint32_t D2VGA_CONTROL;

	uint32_t D3VGA_CONTROL;

	uint32_t D4VGA_CONTROL;

};



#define TG_COMMON_MASK_SH_LIST_DCN(mask_sh)\