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Commit d4f38620 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/net-next 



Jeff Kirsher says:

====================
Intel Wired LAN Driver Updates 2014-06-11

This series contains updates to igb, i40e and i40evf.

Todd makes a change to igb to un-hide invariant returns by getting rid of
the E1000_SUCCESS define and converting those returns to return 0.

Jacob separates the hardware logic from the set function, so that we can
re-use it during a ptp_reset in igb.  This enables the reset to return
functionality to the last know timestamp mode, rather than resetting the
value.

Ashish implements context flags for headwb and headwb_addr so that we
do not have to keep them always enabled.

Shannon updates the admin queue API for the new firmware, which adds
set_pf_content, nvm_config_read/write, replaces set_phy_reset with
set_phy_debug and removes nvm_read/write_reg_se.  Cleans up the driver
to use the stored base_queue value since there is no need to read the
PCI register for the PF's base queue on every single transmit queue
enable and disable as we already have the value stored from reading
the capability features at startup.

Anjali changes the notion of source and destination for FD_SB in ethtool
to align i40e with other drivers.  Adds flow director statistics to
the PF stats.  Fixes a bug in ethtool for flow director drop packet
filter where the drop action comes down as a ring_cookie value, so allow
it as a special value that can be used to configure destination control.

Mitch fixes the i40evf to keep the driver from going down when it is
already in a down state.  This prevents a CPU soft lock in napi_disable().
Also change the i40evf to check the admin queue error bits since the
firmware can indicate any admin queue error states to the driver via
some bits in the length registers.

Neerav separates out the DCB capability and enabled flags because currently
if the firmware reports DCB capability the driver enables
I40E_FLAG_DCB_ENABLED flag.  When this flag is enabled the driver inserts
a tag when transmitting a packet from the port even if there are no DCB
traffic classes configured at the port.  So by adding the additional flag,
I40E_FLAG_DCB_CAPABLE, that will be set when the DCB capability is present
and the existing enabled flag will only be set if there are more than one
traffic classes configured at the port.

Greg fixes the i40e driver to not automatically accept tagged packets by
default so that the system must request a VLAN tag packet filter to get
packets with that tag.  Greg also converts i40e to use the in-kernel
ether_addr_copy() instead of mempcy().

Jesse removes the FTYPE field from the receive descriptor to match the
hardware implementation.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 813ebbbf f8320902

drivers/net/ethernet/intel/i40e/i40e.h

+15 −0
Original line number Diff line number Diff line
@@ -154,11 +154,23 @@ struct i40e_lump_tracking { 
#define I40E_FDIR_BUFFER_FULL_MARGIN	10

#define I40E_FDIR_BUFFER_HEAD_ROOM	200



enum i40e_fd_stat_idx {

	I40E_FD_STAT_ATR,

	I40E_FD_STAT_SB,

	I40E_FD_STAT_PF_COUNT

};

#define I40E_FD_STAT_PF_IDX(pf_id) ((pf_id) * I40E_FD_STAT_PF_COUNT)

#define I40E_FD_ATR_STAT_IDX(pf_id) \

			(I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR)

#define I40E_FD_SB_STAT_IDX(pf_id)  \

			(I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_SB)



struct i40e_fdir_filter {

	struct hlist_node fdir_node;

	/* filter ipnut set */

	u8 flow_type;

	u8 ip4_proto;

	/* TX packet view of src and dst */

	__be32 dst_ip[4];

	__be32 src_ip[4];

	__be16 src_port;
@@ -222,6 +234,8 @@ struct i40e_pf { 


	struct hlist_head fdir_filter_list;

	u16 fdir_pf_active_filters;

	u16 fd_sb_cnt_idx;

	u16 fd_atr_cnt_idx;



#ifdef CONFIG_I40E_VXLAN

	__be16  vxlan_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS];
@@ -263,6 +277,7 @@ struct i40e_pf { 
#ifdef CONFIG_I40E_VXLAN

#define I40E_FLAG_VXLAN_FILTER_SYNC            (u64)(1 << 27)

#endif

#define I40E_FLAG_DCB_CAPABLE                  (u64)(1 << 29)



	/* tracks features that get auto disabled by errors */

	u64 auto_disable_flags;

drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h

+80 −16
Original line number Diff line number Diff line
@@ -34,7 +34,7 @@ 
 */



#define I40E_FW_API_VERSION_MAJOR  0x0001

#define I40E_FW_API_VERSION_MINOR  0x0001

#define I40E_FW_API_VERSION_MINOR  0x0002



struct i40e_aq_desc {

	__le16 flags;
@@ -123,6 +123,7 @@ enum i40e_admin_queue_opc { 
	i40e_aqc_opc_get_version      = 0x0001,

	i40e_aqc_opc_driver_version   = 0x0002,

	i40e_aqc_opc_queue_shutdown   = 0x0003,

	i40e_aqc_opc_set_pf_context   = 0x0004,



	/* resource ownership */

	i40e_aqc_opc_request_resource = 0x0008,
@@ -222,13 +223,15 @@ enum i40e_admin_queue_opc { 
	i40e_aqc_opc_get_partner_advt    = 0x0616,

	i40e_aqc_opc_set_lb_modes        = 0x0618,

	i40e_aqc_opc_get_phy_wol_caps    = 0x0621,

	i40e_aqc_opc_set_phy_reset       = 0x0622,

	i40e_aqc_opc_set_phy_debug	 = 0x0622,

	i40e_aqc_opc_upload_ext_phy_fm   = 0x0625,



	/* NVM commands */

	i40e_aqc_opc_nvm_read         = 0x0701,

	i40e_aqc_opc_nvm_erase        = 0x0702,

	i40e_aqc_opc_nvm_update       = 0x0703,

	i40e_aqc_opc_nvm_config_read  = 0x0704,

	i40e_aqc_opc_nvm_config_write = 0x0705,



	/* virtualization commands */

	i40e_aqc_opc_send_msg_to_pf   = 0x0801,
@@ -270,8 +273,6 @@ enum i40e_admin_queue_opc { 
	i40e_aqc_opc_debug_set_mode         = 0xFF01,

	i40e_aqc_opc_debug_read_reg         = 0xFF03,

	i40e_aqc_opc_debug_write_reg        = 0xFF04,

	i40e_aqc_opc_debug_read_reg_sg      = 0xFF05,

	i40e_aqc_opc_debug_write_reg_sg     = 0xFF06,

	i40e_aqc_opc_debug_modify_reg       = 0xFF07,

	i40e_aqc_opc_debug_dump_internals   = 0xFF08,

	i40e_aqc_opc_debug_modify_internals = 0xFF09,
@@ -339,6 +340,14 @@ struct i40e_aqc_queue_shutdown { 


I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);



/* Set PF context (0x0004, direct) */

struct i40e_aqc_set_pf_context {

	u8	pf_id;

	u8	reserved[15];

};



I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);



/* Request resource ownership (direct 0x0008)

 * Release resource ownership (direct 0x0009)

 */
@@ -1404,11 +1413,12 @@ I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); 
struct i40e_aqc_configure_switching_comp_ets_data {

	u8     reserved[4];

	u8     tc_valid_bits;

	u8     reserved1;

	u8     seepage;

#define I40E_AQ_ETS_SEEPAGE_EN_MASK     0x1

	u8     tc_strict_priority_flags;

	u8     reserved2[17];

	u8     reserved1[17];

	u8     tc_bw_share_credits[8];

	u8     reserved3[96];

	u8     reserved2[96];

};



/* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
@@ -1525,6 +1535,8 @@ enum i40e_aq_phy_type { 
	I40E_PHY_TYPE_XLPPI			= 0x9,

	I40E_PHY_TYPE_40GBASE_CR4_CU		= 0xA,

	I40E_PHY_TYPE_10GBASE_CR1_CU		= 0xB,

	I40E_PHY_TYPE_10GBASE_AOC		= 0xC,

	I40E_PHY_TYPE_40GBASE_AOC		= 0xD,

	I40E_PHY_TYPE_100BASE_TX		= 0x11,

	I40E_PHY_TYPE_1000BASE_T		= 0x12,

	I40E_PHY_TYPE_10GBASE_T			= 0x13,
@@ -1535,7 +1547,10 @@ enum i40e_aq_phy_type { 
	I40E_PHY_TYPE_40GBASE_CR4		= 0x18,

	I40E_PHY_TYPE_40GBASE_SR4		= 0x19,

	I40E_PHY_TYPE_40GBASE_LR4		= 0x1A,

	I40E_PHY_TYPE_20GBASE_KR2		= 0x1B,

	I40E_PHY_TYPE_1000BASE_SX		= 0x1B,

	I40E_PHY_TYPE_1000BASE_LX		= 0x1C,

	I40E_PHY_TYPE_1000BASE_T_OPTICAL	= 0x1D,

	I40E_PHY_TYPE_20GBASE_KR2		= 0x1E,

	I40E_PHY_TYPE_MAX

};
@@ -1679,6 +1694,7 @@ struct i40e_aqc_get_link_status { 
#define I40E_AQ_LINK_TX_ACTIVE       0x00

#define I40E_AQ_LINK_TX_DRAINED      0x01

#define I40E_AQ_LINK_TX_FLUSHED      0x03

#define I40E_AQ_LINK_FORCED_40G      0x10

	u8     loopback;         /* use defines from i40e_aqc_set_lb_mode */

	__le16 max_frame_size;

	u8     config;
@@ -1730,14 +1746,21 @@ struct i40e_aqc_set_lb_mode { 


I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);



/* Set PHY Reset command (0x0622) */

struct i40e_aqc_set_phy_reset {

	u8     reset_flags;

#define I40E_AQ_PHY_RESET_REQUEST  0x02

/* Set PHY Debug command (0x0622) */

struct i40e_aqc_set_phy_debug {

	u8     command_flags;

#define I40E_AQ_PHY_DEBUG_RESET_INTERNAL	0x02

#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT	2

#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK	(0x03 << \

					I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)

#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE	0x00

#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD	0x01

#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT	0x02

#define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW	0x10

	u8     reserved[15];

};



I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_reset);

I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);



enum i40e_aq_phy_reg_type {

	I40E_AQC_PHY_REG_INTERNAL         = 0x1,
@@ -1762,6 +1785,47 @@ struct i40e_aqc_nvm_update { 


I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);



/* NVM Config Read (indirect 0x0704) */

struct i40e_aqc_nvm_config_read {

	__le16 cmd_flags;

#define ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK	1

#define ANVM_READ_SINGLE_FEATURE		0

#define ANVM_READ_MULTIPLE_FEATURES		1

	__le16 element_count;

	__le16 element_id;		/* Feature/field ID */

	u8     reserved[2];

	__le32 address_high;

	__le32 address_low;

};



I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);



/* NVM Config Write (indirect 0x0705) */

struct i40e_aqc_nvm_config_write {

	__le16 cmd_flags;

	__le16 element_count;

	u8     reserved[4];

	__le32 address_high;

	__le32 address_low;

};



I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);



struct i40e_aqc_nvm_config_data_feature {

	__le16 feature_id;

	__le16 instance_id;

	__le16 feature_options;

	__le16 feature_selection;

};



struct i40e_aqc_nvm_config_data_immediate_field {

#define ANVM_FEATURE_OR_IMMEDIATE_MASK	0x2

	__le16 field_id;

	__le16 instance_id;

	__le16 field_options;

	__le16 field_value;

};



/* Send to PF command (indirect 0x0801) id is only used by PF

 * Send to VF command (indirect 0x0802) id is only used by PF

 * Send to Peer PF command (indirect 0x0803)

drivers/net/ethernet/intel/i40e/i40e_common.c

+2 −3
Original line number Diff line number Diff line
@@ -665,10 +665,9 @@ i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 
 **/

void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)

{

	u32 reg_val = rd32(hw, I40E_PFLAN_QALLOC);

	u32 first_queue = (reg_val & I40E_PFLAN_QALLOC_FIRSTQ_MASK);

	u32 abs_queue_idx = first_queue + queue;

	u32 abs_queue_idx = hw->func_caps.base_queue + queue;

	u32 reg_block = 0;

	u32 reg_val;



	if (abs_queue_idx >= 128)

		reg_block = abs_queue_idx / 128;

drivers/net/ethernet/intel/i40e/i40e_dcb_nl.c

+2 −2
Original line number Diff line number Diff line
@@ -302,8 +302,8 @@ void i40e_dcbnl_setup(struct i40e_vsi *vsi) 
	struct net_device *dev = vsi->netdev;

	struct i40e_pf *pf = i40e_netdev_to_pf(dev);



	/* DCB not enabled */

	if (!(pf->flags & I40E_FLAG_DCB_ENABLED))

	/* Not DCB capable */

	if (!(pf->flags & I40E_FLAG_DCB_CAPABLE))

		return;



	/* Do not setup DCB NL ops for MFP mode */

drivers/net/ethernet/intel/i40e/i40e_ethtool.c

+26 −11
Original line number Diff line number Diff line
@@ -145,6 +145,9 @@ static struct i40e_stats i40e_gstrings_stats[] = { 
	I40E_PF_STAT("rx_jabber", stats.rx_jabber),

	I40E_PF_STAT("VF_admin_queue_requests", vf_aq_requests),

	I40E_PF_STAT("rx_hwtstamp_cleared", rx_hwtstamp_cleared),

	I40E_PF_STAT("fdir_atr_match", stats.fd_atr_match),

	I40E_PF_STAT("fdir_sb_match", stats.fd_sb_match),



	/* LPI stats */

	I40E_PF_STAT("tx_lpi_status", stats.tx_lpi_status),

	I40E_PF_STAT("rx_lpi_status", stats.rx_lpi_status),
@@ -1249,10 +1252,17 @@ static int i40e_get_ethtool_fdir_entry(struct i40e_pf *pf, 
		fsp->m_u.usr_ip4_spec.proto = 0;

	}



	fsp->h_u.tcp_ip4_spec.psrc = rule->src_port;

	fsp->h_u.tcp_ip4_spec.pdst = rule->dst_port;

	fsp->h_u.tcp_ip4_spec.ip4src = rule->src_ip[0];

	fsp->h_u.tcp_ip4_spec.ip4dst = rule->dst_ip[0];

	/* Reverse the src and dest notion, since the HW views them from

	 * Tx perspective where as the user expects it from Rx filter view.

	 */

	fsp->h_u.tcp_ip4_spec.psrc = rule->dst_port;

	fsp->h_u.tcp_ip4_spec.pdst = rule->src_port;

	fsp->h_u.tcp_ip4_spec.ip4src = rule->dst_ip[0];

	fsp->h_u.tcp_ip4_spec.ip4dst = rule->src_ip[0];



	if (rule->dest_ctl == I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET)

		fsp->ring_cookie = RX_CLS_FLOW_DISC;

	else

		fsp->ring_cookie = rule->q_index;



	return 0;
@@ -1557,7 +1567,8 @@ static int i40e_add_fdir_ethtool(struct i40e_vsi *vsi, 
		return -EINVAL;

	}



	if (fsp->ring_cookie >= vsi->num_queue_pairs)

	if ((fsp->ring_cookie != RX_CLS_FLOW_DISC) &&

	    (fsp->ring_cookie >= vsi->num_queue_pairs))

		return -EINVAL;



	input = kzalloc(sizeof(*input), GFP_KERNEL);
@@ -1578,13 +1589,17 @@ static int i40e_add_fdir_ethtool(struct i40e_vsi *vsi, 
	input->pctype = 0;

	input->dest_vsi = vsi->id;

	input->fd_status = I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID;

	input->cnt_index = 0;

	input->cnt_index  = pf->fd_sb_cnt_idx;

	input->flow_type = fsp->flow_type;

	input->ip4_proto = fsp->h_u.usr_ip4_spec.proto;

	input->src_port = fsp->h_u.tcp_ip4_spec.psrc;

	input->dst_port = fsp->h_u.tcp_ip4_spec.pdst;

	input->src_ip[0] = fsp->h_u.tcp_ip4_spec.ip4src;

	input->dst_ip[0] = fsp->h_u.tcp_ip4_spec.ip4dst;



	/* Reverse the src and dest notion, since the HW expects them to be from

	 * Tx perspective where as the input from user is from Rx filter view.

	 */

	input->dst_port = fsp->h_u.tcp_ip4_spec.psrc;

	input->src_port = fsp->h_u.tcp_ip4_spec.pdst;

	input->dst_ip[0] = fsp->h_u.tcp_ip4_spec.ip4src;

	input->src_ip[0] = fsp->h_u.tcp_ip4_spec.ip4dst;



	ret = i40e_add_del_fdir(vsi, input, true);

	if (ret)