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Commit d45fd24d authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/radeon: use HDP_MEM_COHERENCY_FLUSH_CNTL for sdma as well 



The new HDP flush method doesn't seem to work reliably on
sDMA either, so use the old method here too.

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 520a8718

drivers/gpu/drm/radeon/cik_sdma.c

+12 −28
Original line number Diff line number Diff line
@@ -102,14 +102,6 @@ void cik_sdma_fence_ring_emit(struct radeon_device *rdev, 
{

	struct radeon_ring *ring = &rdev->ring[fence->ring];

	u64 addr = rdev->fence_drv[fence->ring].gpu_addr;

	u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) |

			  SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */

	u32 ref_and_mask;



	if (fence->ring == R600_RING_TYPE_DMA_INDEX)

		ref_and_mask = SDMA0;

	else

		ref_and_mask = SDMA1;



	/* write the fence */

	radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
@@ -119,12 +111,12 @@ void cik_sdma_fence_ring_emit(struct radeon_device *rdev, 
	/* generate an interrupt */

	radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));

	/* flush HDP */

	radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));

	radeon_ring_write(ring, GPU_HDP_FLUSH_DONE);

	radeon_ring_write(ring, GPU_HDP_FLUSH_REQ);

	radeon_ring_write(ring, ref_and_mask); /* REFERENCE */

	radeon_ring_write(ring, ref_and_mask); /* MASK */

	radeon_ring_write(ring, (4 << 16) | 10); /* RETRY_COUNT, POLL_INTERVAL */

	/* We should be using the new POLL_REG_MEM special op packet here

	 * but it causes sDMA to hang sometimes

	 */

	radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));

	radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);

	radeon_ring_write(ring, 0);

}



/**
@@ -720,18 +712,10 @@ void cik_sdma_vm_set_page(struct radeon_device *rdev, 
void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)

{

	struct radeon_ring *ring = &rdev->ring[ridx];

	u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) |

			  SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */

	u32 ref_and_mask;



	if (vm == NULL)

		return;



	if (ridx == R600_RING_TYPE_DMA_INDEX)

		ref_and_mask = SDMA0;

	else

		ref_and_mask = SDMA1;



	radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));

	if (vm->id < 8) {

		radeon_ring_write(ring, (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2);
@@ -766,12 +750,12 @@ void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm 
	radeon_ring_write(ring, VMID(0));



	/* flush HDP */

	radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));

	radeon_ring_write(ring, GPU_HDP_FLUSH_DONE);

	radeon_ring_write(ring, GPU_HDP_FLUSH_REQ);

	radeon_ring_write(ring, ref_and_mask); /* REFERENCE */

	radeon_ring_write(ring, ref_and_mask); /* MASK */

	radeon_ring_write(ring, (4 << 16) | 10); /* RETRY_COUNT, POLL_INTERVAL */

	/* We should be using the new POLL_REG_MEM special op packet here

	 * but it causes sDMA to hang sometimes

	 */

	radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));

	radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);

	radeon_ring_write(ring, 0);



	/* flush TLB */

	radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));