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Commit d3f15dbd authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'bcm7xxx-next' 



Florian Fainelli says:

====================
net: phy: bcm7xxx: workaround updates

This patch series contains some updates to the Broadcom BCM7xxx internal
PHY driver, including:

- removing an annonying print that would appear during interface up/down and
  suspend/resume cycles
- drop a workaround sequence for a non-production PHY revision
- add new workarounds for the latest and greatest PHY devices found out there
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 955a9d20 0c2fdc25

drivers/net/phy/bcm7xxx.c

+90 −44
Original line number Diff line number Diff line
@@ -39,45 +39,15 @@ 


#define AFE_RXCONFIG_0			MISC_ADDR(0x38, 0)

#define AFE_RXCONFIG_1			MISC_ADDR(0x38, 1)

#define AFE_RXCONFIG_2			MISC_ADDR(0x38, 2)

#define AFE_RX_LP_COUNTER		MISC_ADDR(0x38, 3)

#define AFE_TX_CONFIG			MISC_ADDR(0x39, 0)

#define AFE_VDCA_ICTRL_0		MISC_ADDR(0x39, 1)

#define AFE_VDAC_OTHERS_0		MISC_ADDR(0x39, 3)

#define AFE_HPF_TRIM_OTHERS		MISC_ADDR(0x3a, 0)



#define CORE_EXPB0			0xb0



static int bcm7445_config_init(struct phy_device *phydev)

{

	int ret;

	const struct bcm7445_regs {

		int reg;

		u16 value;

	} bcm7445_regs_cfg[] = {

		/* increases ADC latency by 24ns */

		{ MII_BCM54XX_EXP_SEL, 0x0038 },

		{ MII_BCM54XX_EXP_DATA, 0xAB95 },

		/* increases internal 1V LDO voltage by 5% */

		{ MII_BCM54XX_EXP_SEL, 0x2038 },

		{ MII_BCM54XX_EXP_DATA, 0xBB22 },

		/* reduce RX low pass filter corner frequency */

		{ MII_BCM54XX_EXP_SEL, 0x6038 },

		{ MII_BCM54XX_EXP_DATA, 0xFFC5 },

		/* reduce RX high pass filter corner frequency */

		{ MII_BCM54XX_EXP_SEL, 0x003a },

		{ MII_BCM54XX_EXP_DATA, 0x2002 },

	};

	unsigned int i;



	for (i = 0; i < ARRAY_SIZE(bcm7445_regs_cfg); i++) {

		ret = phy_write(phydev,

				bcm7445_regs_cfg[i].reg,

				bcm7445_regs_cfg[i].value);

		if (ret)

			return ret;

	}



	return 0;

}



static void phy_write_exp(struct phy_device *phydev,

					u16 reg, u16 value)

{
@@ -102,7 +72,16 @@ static void phy_write_misc(struct phy_device *phydev, 
	phy_write(phydev, MII_BCM54XX_EXP_DATA, value);

}



static int bcm7xxx_28nm_afe_config_init(struct phy_device *phydev)

static void r_rc_cal_reset(struct phy_device *phydev)

{

	/* Reset R_CAL/RC_CAL Engine */

	phy_write_exp(phydev, 0x00b0, 0x0010);



	/* Disable Reset R_AL/RC_CAL Engine */

	phy_write_exp(phydev, 0x00b0, 0x0000);

}



static int bcm7xxx_28nm_b0_afe_config_init(struct phy_device *phydev)

{

	/* Increase VCO range to prevent unlocking problem of PLL at low

	 * temp
@@ -123,11 +102,7 @@ static int bcm7xxx_28nm_afe_config_init(struct phy_device *phydev) 
	/* Switch to CORE_BASE1E */

	phy_write(phydev, MII_BCM7XXX_CORE_BASE1E, 0xd);



	/* Reset R_CAL/RC_CAL Engine */

	phy_write_exp(phydev, CORE_EXPB0, 0x0010);



	/* Disable Reset R_CAL/RC_CAL Engine */

	phy_write_exp(phydev, CORE_EXPB0, 0x0000);

	r_rc_cal_reset(phydev);



	/* write AFE_RXCONFIG_0 */

	phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb19);
@@ -147,6 +122,71 @@ static int bcm7xxx_28nm_afe_config_init(struct phy_device *phydev) 
	return 0;

}



static int bcm7xxx_28nm_d0_afe_config_init(struct phy_device *phydev)

{

	/* AFE_RXCONFIG_0 */

	phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb15);



	/* AFE_RXCONFIG_1 */

	phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f);



	/* AFE_RXCONFIG_2, set rCal offset for HT=0 code and LT=-2 code */

	phy_write_misc(phydev, AFE_RXCONFIG_2, 0x2003);



	/* AFE_RX_LP_COUNTER, set RX bandwidth to maximum */

	phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0);



	/* AFE_TX_CONFIG, set 1000BT Cfeed=110 for all ports */

	phy_write_misc(phydev, AFE_TX_CONFIG, 0x0061);



	/* AFE_VDCA_ICTRL_0, set Iq=1101 instead of 0111 for AB symmetry */

	phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da);



	/* AFE_VDAC_OTHERS_0, set 1000BT Cidac=010 for all ports */

	phy_write_misc(phydev, AFE_VDAC_OTHERS_0, 0xa020);



	/* AFE_HPF_TRIM_OTHERS, set 100Tx/10BT to -4.5% swing and set rCal

	 * offset for HT=0 code

	 */

	phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3);



	/* CORE_BASE1E, force trim to overwrite and set I_ext trim to 0000 */

	phy_write(phydev, MII_BCM7XXX_CORE_BASE1E, 0x0010);



	/* DSP_TAP10, adjust bias current trim (+0% swing, +0 tick) */

	phy_write_misc(phydev, DSP_TAP10, 0x011b);



	/* Reset R_CAL/RC_CAL engine */

	r_rc_cal_reset(phydev);



	return 0;

}



static int bcm7xxx_28nm_e0_plus_afe_config_init(struct phy_device *phydev)

{

	/* AFE_RXCONFIG_1, provide more margin for INL/DNL measurement */

	phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f);



	/* AFE_VDCA_ICTRL_0, set Iq=1101 instead of 0111 for AB symmetry */

	phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da);



	/* AFE_HPF_TRIM_OTHERS, set 100Tx/10BT to -4.5% swing and set rCal

	 * offset for HT=0 code

	 */

	phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3);



	/* CORE_BASE1E, force trim to overwrite and set I_ext trim to 0000 */

	phy_write(phydev, MII_BCM7XXX_CORE_BASE1E, 0x0010);



	/* DSP_TAP10, adjust bias current trim (+0% swing, +0 tick) */

	phy_write_misc(phydev, DSP_TAP10, 0x011b);



	/* Reset R_CAL/RC_CAL engine */

	r_rc_cal_reset(phydev);



	return 0;

}



static int bcm7xxx_apd_enable(struct phy_device *phydev)

{

	int val;
@@ -200,15 +240,21 @@ static int bcm7xxx_28nm_config_init(struct phy_device *phydev) 
	u8 patch = PHY_BRCM_7XXX_PATCH(phydev->dev_flags);

	int ret = 0;



	dev_info(&phydev->dev, "PHY revision: 0x%02x, patch: %d\n", rev, patch);

	pr_info_once("%s: %s PHY revision: 0x%02x, patch: %d\n",

		     dev_name(&phydev->dev), phydev->drv->name, rev, patch);



	switch (rev) {

	case 0xa0:

	case 0xb0:

		ret = bcm7445_config_init(phydev);

		ret = bcm7xxx_28nm_b0_afe_config_init(phydev);

		break;

	case 0xd0:

		ret = bcm7xxx_28nm_d0_afe_config_init(phydev);

		break;

	case 0xe0:

	case 0xf0:

		ret = bcm7xxx_28nm_e0_plus_afe_config_init(phydev);

		break;

	default:

		ret = bcm7xxx_28nm_afe_config_init(phydev);

		break;

	}
@@ -336,7 +382,7 @@ static int bcm7xxx_dummy_config_init(struct phy_device *phydev) 
	.features	= PHY_GBIT_FEATURES |				\

			  SUPPORTED_Pause | SUPPORTED_Asym_Pause,	\

	.flags		= PHY_IS_INTERNAL,				\

	.config_init	= bcm7xxx_28nm_afe_config_init,			\

	.config_init	= bcm7xxx_28nm_config_init,			\

	.config_aneg	= genphy_config_aneg,				\

	.read_status	= genphy_read_status,				\

	.resume		= bcm7xxx_28nm_resume,				\