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Commit d3e51161 authored by Heiko Stübner's avatar Heiko Stübner Committed by Linus Walleij
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pinctrl: add pinctrl driver for Rockchip SoCs 



This driver adds support the Cortex-A9 based SoCs from Rockchip,
so at least the RK2928, RK3066 (a and b) and RK3188.
Earlier Rockchip SoCs seem to use similar mechanics for gpio
handling so should be supportable with relative small changes.
Pull handling on the rk3188 is currently a stub, due to it being
a bit different to the earlier SoCs.

Pinmuxing as well as gpio (and interrupt-) handling tested on
a rk3066a based machine.

Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 7db9af4b

Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt

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* Rockchip Pinmux Controller



The Rockchip Pinmux Controller, enables the IC

to share one PAD to several functional blocks. The sharing is done by

multiplexing the PAD input/output signals. For each PAD there are up to

4 muxing options with option 0 being the use as a GPIO.



Please refer to pinctrl-bindings.txt in this directory for details of the

common pinctrl bindings used by client devices, including the meaning of the

phrase "pin configuration node".



The Rockchip pin configuration node is a node of a group of pins which can be

used for a specific device or function. This node represents both mux and

config of the pins in that group. The 'pins' selects the function mode(also

named pin mode) this pin can work on and the 'config' configures various pad

settings such as pull-up, etc.



The pins are grouped into up to 5 individual pin banks which need to be

defined as gpio sub-nodes of the pinmux controller.



Required properties for iomux controller:

  - compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl"

		       "rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl"



Required properties for gpio sub nodes:

  - compatible: "rockchip,gpio-bank"

  - reg: register of the gpio bank (different than the iomux registerset)

  - interrupts: base interrupt of the gpio bank in the interrupt controller

  - clocks: clock that drives this bank

  - gpio-controller: identifies the node as a gpio controller and pin bank.

  - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO

    binding is used, the amount of cells must be specified as 2. See generic

    GPIO binding documentation for description of particular cells.

  - interrupt-controller: identifies the controller node as interrupt-parent.

  - #interrupt-cells: the value of this property should be 2 and the interrupt

    cells should use the standard two-cell scheme described in

    bindings/interrupt-controller/interrupts.txt



Required properties for pin configuration node:

  - rockchip,pins: 3 integers array, represents a group of pins mux and config

    setting. The format is rockchip,pins = <PIN_BANK PIN_BANK_IDX MUX &phandle>.

    The MUX 0 means gpio and MUX 1 to 3 mean the specific device function.

    The phandle of a node containing the generic pinconfig options

    to use, as described in pinctrl-bindings.txt in this directory.



Examples:



#include <dt-bindings/pinctrl/rockchip.h>



...



pinctrl@20008000 {

	compatible = "rockchip,rk3066a-pinctrl";

	reg = <0x20008000 0x150>;

	#address-cells = <1>;

	#size-cells = <1>;

	ranges;



	gpio0: gpio0@20034000 {

		compatible = "rockchip,gpio-bank";

		reg = <0x20034000 0x100>;

		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&clk_gates8 9>;



		gpio-controller;

		#gpio-cells = <2>;



		interrupt-controller;

		#interrupt-cells = <2>;

	};



	...



	pcfg_pull_default: pcfg_pull_default {

		bias-pull-pin-default

	};



	uart2 {

		uart2_xfer: uart2-xfer {

			rockchip,pins = <RK_GPIO1 8 1 &pcfg_pull_default>,

					<RK_GPIO1 9 1 &pcfg_pull_default>;

		};

	};

};



uart2: serial@20064000 {

	compatible = "snps,dw-apb-uart";

	reg = <0x20064000 0x400>;

	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;

	reg-shift = <2>;

	reg-io-width = <1>;

	clocks = <&mux_uart2>;

	status = "okay";



	pinctrl-names = "default";

	pinctrl-0 = <&uart2_xfer>;

};

drivers/pinctrl/Kconfig

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@@ -158,6 +158,12 @@ config PINCTRL_DB8540 
	bool "DB8540 pin controller driver"

	depends on PINCTRL_NOMADIK && ARCH_U8500



config PINCTRL_ROCKCHIP

	bool

	select PINMUX

	select GENERIC_PINCONF

	select GENERIC_IRQ_CHIP



config PINCTRL_SINGLE

	tristate "One-register-per-pin type device tree based pinctrl driver"

	depends on OF

drivers/pinctrl/Makefile

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@@ -31,6 +31,7 @@ obj-$(CONFIG_PINCTRL_NOMADIK) += pinctrl-nomadik.o 
obj-$(CONFIG_PINCTRL_STN8815)	+= pinctrl-nomadik-stn8815.o

obj-$(CONFIG_PINCTRL_DB8500)	+= pinctrl-nomadik-db8500.o

obj-$(CONFIG_PINCTRL_DB8540)	+= pinctrl-nomadik-db8540.o

obj-$(CONFIG_PINCTRL_ROCKCHIP)	+= pinctrl-rockchip.o

obj-$(CONFIG_PINCTRL_SINGLE)	+= pinctrl-single.o

obj-$(CONFIG_PINCTRL_SIRF)	+= sirf/

obj-$(CONFIG_PINCTRL_SUNXI)	+= pinctrl-sunxi.o

drivers/pinctrl/pinctrl-rockchip.c

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File added.

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include/dt-bindings/pinctrl/rockchip.h

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/*

 * Header providing constants for Rockchip pinctrl bindings.

 *

 * Copyright (c) 2013 MundoReader S.L.

 * Author: Heiko Stuebner <heiko@sntech.de>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#ifndef __DT_BINDINGS_ROCKCHIP_PINCTRL_H__

#define __DT_BINDINGS_ROCKCHIP_PINCTRL_H__



#define RK_GPIO0	0

#define RK_GPIO1	1

#define RK_GPIO2	2

#define RK_GPIO3	3

#define RK_GPIO4	4

#define RK_GPIO6	6



#define RK_FUNC_GPIO	0

#define RK_FUNC_1	1

#define RK_FUNC_2	2



#endif