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Commit d3964221 authored by Ganapatrao Kulkarni's avatar Ganapatrao Kulkarni Committed by Arnaldo Carvalho de Melo
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perf vendor events arm64: Add ThunderX2 implementation defined pmu core events 



This is not a full event list, but a short list of useful events.

Signed-off-by: default avatarGanapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
Acked-by: default avatarWill Deacon <will.deacon@arm.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Ganapatrao Kulkarni <gklkml16@gmail.com>
Cc: Jayachandran C <jnair@caviumnetworks.com>
Cc: Jonathan Cameron <jonathan.cameron@huawei.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Robert Richter <robert.richter@cavium.com>
Cc: Shaokun Zhang <zhangshaokun@hisilicon.com>
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/20171016183222.25750-5-ganapatrao.kulkarni@cavium.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 14b22ae0

tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json

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[

    {

        "PublicDescription": "Attributable Level 1 data cache access, read",

        "EventCode": "0x40",

        "EventName": "l1d_cache_rd",

        "BriefDescription": "L1D cache read",

    },

    {

        "PublicDescription": "Attributable Level 1 data cache access, write ",

        "EventCode": "0x41",

        "EventName": "l1d_cache_wr",

        "BriefDescription": "L1D cache write",

    },

    {

        "PublicDescription": "Attributable Level 1 data cache refill, read",

        "EventCode": "0x42",

        "EventName": "l1d_cache_refill_rd",

        "BriefDescription": "L1D cache refill read",

    },

    {

        "PublicDescription": "Attributable Level 1 data cache refill, write",

        "EventCode": "0x43",

        "EventName": "l1d_cache_refill_wr",

        "BriefDescription": "L1D refill write",

    },

    {

        "PublicDescription": "Attributable Level 1 data TLB refill, read",

        "EventCode": "0x4C",

        "EventName": "l1d_tlb_refill_rd",

        "BriefDescription": "L1D tlb refill read",

    },

    {

        "PublicDescription": "Attributable Level 1 data TLB refill, write",

        "EventCode": "0x4D",

        "EventName": "l1d_tlb_refill_wr",

        "BriefDescription": "L1D tlb refill write",

    },

    {

        "PublicDescription": "Attributable Level 1 data or unified TLB access, read",

        "EventCode": "0x4E",

        "EventName": "l1d_tlb_rd",

        "BriefDescription": "L1D tlb read",

    },

    {

        "PublicDescription": "Attributable Level 1 data or unified TLB access, write",

        "EventCode": "0x4F",

        "EventName": "l1d_tlb_wr",

        "BriefDescription": "L1D tlb write",

    },

    {

        "PublicDescription": "Bus access read",

        "EventCode": "0x60",

        "EventName": "bus_access_rd",

        "BriefDescription": "Bus access read",

   },

   {

        "PublicDescription": "Bus access write",

        "EventCode": "0x61",

        "EventName": "bus_access_wr",

        "BriefDescription": "Bus access write",

   }

]

tools/perf/pmu-events/arch/arm64/mapfile.csv

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# Format:

#	MIDR,Version,JSON/file/pathname,Type

#

# where

#	MIDR	Processor version

#		Variant[23:20] and Revision [3:0] should be zero.

#	Version could be used to track version of of JSON file

#		but currently unused.

#	JSON/file/pathname is the path to JSON file, relative

#		to tools/perf/pmu-events/arch/arm64/.

#	Type is core, uncore etc

#

#

#Family-model,Version,Filename,EventType

0x00000000420f5160,v1,cavium,core