Merge branch 'msm-next' of git://people.freedesktop.org/~robclark/linux into drm-next

  be 0 or 1, since we have 2 DSI controllers at most for now.

- interrupts: The interrupt signal from the DSI block.

- power-domains: Should be <&mmcc MDSS_GDSC>.

- clocks: device clocks

  See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.

- clocks: Phandles to device clocks.

- clock-names: the following clocks are required:

  * "mdp_core_clk"

  * "iface_clk"

  * "core_clk"

  For DSIv2, we need an additional clock:

   * "src_clk"

- assigned-clocks: Parents of "byte_clk" and "pixel_clk" for the given platform.

- assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided

  by a DSI PHY block. See [1] for details on clock bindings.

- vdd-supply: phandle to vdd regulator device node

- vddio-supply: phandle to vdd-io regulator device node

- vdda-supply: phandle to vdda regulator device node

- qcom,dsi-phy: phandle to DSI PHY device node

- phys: phandle to DSI PHY device node

- phy-names: the name of the corresponding PHY device

- syscon-sfpb: A phandle to mmss_sfpb syscon node (only for DSIv2)

- ports: Contains 2 DSI controller ports as child nodes. Each port contains

  an endpoint subnode as defined in [2] and [3].

Optional properties:

- panel@0: Node of panel connected to this DSI controller.

  See files in Documentation/devicetree/bindings/display/panel/ for each supported

  panel.

  See files in [4] for each supported panel.

- qcom,dual-dsi-mode: Boolean value indicating if the DSI controller is

  driving a panel which needs 2 DSI links.

- qcom,master-dsi: Boolean value indicating if the DSI controller is driving

- pinctrl-names: the pin control state names; should contain "default"

- pinctrl-0: the default pinctrl state (active)

- pinctrl-n: the "sleep" pinctrl state

- port: DSI controller output port, containing one endpoint subnode.

- ports: contains DSI controller input and output ports as children, each

  containing one endpoint subnode.

  DSI Endpoint properties:

  - remote-endpoint: set to phandle of the connected panel's endpoint.

    See Documentation/devicetree/bindings/graph.txt for device graph info.

  - qcom,data-lane-map: this describes how the logical DSI lanes are mapped

    to the physical lanes on the given platform. The value contained in

    index n describes what logical data lane is mapped to the physical data

    lane n (DATAn, where n lies between 0 and 3).

  - remote-endpoint: For port@0, set to phandle of the connected panel/bridge's

    input endpoint. For port@1, set to the MDP interface output. See [2] for

    device graph info.

  - data-lanes: this describes how the physical DSI data lanes are mapped

    to the logical lanes on the given platform. The value contained in

    index n describes what physical lane is mapped to the logical lane n

    (DATAn, where n lies between 0 and 3). The clock lane position is fixed

    and can't be changed. Hence, they aren't a part of the DT bindings. See

    [3] for more info on the data-lanes property.

    For example:

    qcom,data-lane-map = <3 0 1 2>;

    data-lanes = <3 0 1 2>;

    The above mapping describes that the logical data lane DATA3 is mapped to

    the physical data lane DATA0, logical DATA0 to physical DATA1, logic DATA1

    to phys DATA2 and logic DATA2 to phys DATA3.

    The above mapping describes that the logical data lane DATA0 is mapped to

    the physical data lane DATA3, logical DATA1 to physical DATA0, logic DATA2

    to phys DATA1 and logic DATA3 to phys DATA2.

    There are only a limited number of physical to logical mappings possible:

    "0123": Logic 0->Phys 0; Logic 1->Phys 1; Logic 2->Phys 2; Logic 3->Phys 3;

    "3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3;

    "2301": Logic 2->Phys 0; Logic 3->Phys 1; Logic 0->Phys 2; Logic 1->Phys 3;

    "1230": Logic 1->Phys 0; Logic 2->Phys 1; Logic 3->Phys 2; Logic 0->Phys 3;

    "0321": Logic 0->Phys 0; Logic 3->Phys 1; Logic 2->Phys 2; Logic 1->Phys 3;

    "1032": Logic 1->Phys 0; Logic 0->Phys 1; Logic 3->Phys 2; Logic 2->Phys 3;

    "2103": Logic 2->Phys 0; Logic 1->Phys 1; Logic 0->Phys 2; Logic 3->Phys 3;

    "3210": Logic 3->Phys 0; Logic 2->Phys 1; Logic 1->Phys 2; Logic 0->Phys 3;

    <0 1 2 3>

    <1 2 3 0>

    <2 3 0 1>

    <3 0 1 2>

    <0 3 2 1>

    <1 0 3 2>

    <2 1 0 3>

    <3 2 1 0>

DSI PHY:

Required properties:

  * "dsi_pll"

  * "dsi_phy"

  * "dsi_phy_regulator"

- clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating

  2 clocks: A byte clock (index 0), and a pixel clock (index 1).

- qcom,dsi-phy-index: The ID of DSI PHY hardware instance. This should

  be 0 or 1, since we have 2 DSI PHYs at most for now.

- power-domains: Should be <&mmcc MDSS_GDSC>.

- clocks: device clocks

  See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.

- clocks: Phandles to device clocks. See [1] for details on clock bindings.

- clock-names: the following clocks are required:

  * "iface_clk"

- vddio-supply: phandle to vdd-io regulator device node

- qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY

  regulator is wanted.

[1] Documentation/devicetree/bindings/clocks/clock-bindings.txt

[2] Documentation/devicetree/bindings/graph.txt

[3] Documentation/devicetree/bindings/media/video-interfaces.txt

[4] Documentation/devicetree/bindings/display/panel/

Example:

	mdss_dsi0: qcom,mdss_dsi@fd922800 {

	dsi0: dsi@fd922800 {

		compatible = "qcom,mdss-dsi-ctrl";

		qcom,dsi-host-index = <0>;

		interrupt-parent = <&mdss_mdp>;

		interrupt-parent = <&mdp>;

		interrupts = <4 0>;

		reg-names = "dsi_ctrl";

		reg = <0xfd922800 0x200>;

			<&mmcc MDSS_AHB_CLK>,

			<&mmcc MDSS_MDP_CLK>,

			<&mmcc MDSS_PCLK0_CLK>;

		assigned-clocks =

				 <&mmcc BYTE0_CLK_SRC>,

				 <&mmcc PCLK0_CLK_SRC>;

		assigned-clock-parents =

				 <&dsi_phy0 0>,

				 <&dsi_phy0 1>;

		vdda-supply = <&pma8084_l2>;

		vdd-supply = <&pma8084_l22>;

		vddio-supply = <&pma8084_l12>;

		qcom,dsi-phy = <&mdss_dsi_phy0>;

		phys = <&dsi_phy0>;

		phy-names ="dsi-phy";

		qcom,dual-dsi-mode;

		qcom,master-dsi;

		qcom,sync-dual-dsi;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&mdss_dsi_active>;

		pinctrl-1 = <&mdss_dsi_suspend>;

		pinctrl-0 = <&dsi_active>;

		pinctrl-1 = <&dsi_suspend>;

		ports {

			#address-cells = <1>;

			#size-cells = <0>;

			port@0 {

				reg = <0>;

				dsi0_in: endpoint {

					remote-endpoint = <&mdp_intf1_out>;

				};

			};

			port@1 {

				reg = <1>;

				dsi0_out: endpoint {

					remote-endpoint = <&panel_in>;

					data-lanes = <0 1 2 3>;

				};

			};

		};

		panel: panel@0 {

			compatible = "sharp,lq101r1sx01";

				};

			};

		};

		port {

			dsi0_out: endpoint {

				remote-endpoint = <&panel_in>;

				lanes = <0 1 2 3>;

			};

		};

	};

	mdss_dsi_phy0: qcom,mdss_dsi_phy@fd922a00 {

	dsi_phy0: dsi-phy@fd922a00 {

		compatible = "qcom,dsi-phy-28nm-hpm";

		qcom,dsi-phy-index = <0>;

		reg-names =

			<0xfd922d80 0x7b>;

		clock-names = "iface_clk";

		clocks = <&mmcc MDSS_AHB_CLK>;

		#clock-cells = <1>;

		vddio-supply = <&pma8084_l12>;

		qcom,dsi-phy-regulator-ldo-mode;

Qualcomm adreno/snapdragon display controller

Qualcomm adreno/snapdragon MDP4 display controller

Description:

This is the bindings documentation for the MDP4 display controller found in

SoCs like MSM8960, APQ8064 and MSM8660.

Required properties:

- compatible:

  * "qcom,mdp4" - mdp4

  * "qcom,mdp5" - mdp5

- reg: Physical base address and length of the controller's registers.

- interrupts: The interrupt signal from the display controller.

- connectors: array of phandles for output device(s)

- clocks: device clocks

  See ../clocks/clock-bindings.txt for details.

- clock-names: the following clocks are required.

  For MDP4:

  * "core_clk"

  * "iface_clk"

  * "bus_clk"

  * "lut_clk"

   * "src_clk"

  * "hdmi_clk"

   * "mdp_clk"

  For MDP5:

   * "bus_clk"

   * "iface_clk"

   * "core_clk_src"

   * "core_clk"

   * "lut_clk" (some MDP5 versions may not need this)

   * "vsync_clk"

  * "tv_clk"

- ports: contains the list of output ports from MDP. These connect to interfaces

  that are external to the MDP hardware, such as HDMI, DSI, EDP etc (LVDS is a

  special case since it is a part of the MDP block itself).

  Each output port contains an endpoint that describes how it is connected to an

  external interface. These are described by the standard properties documented

  here:

	Documentation/devicetree/bindings/graph.txt

	Documentation/devicetree/bindings/media/video-interfaces.txt

  The output port mappings are:

	Port 0 -> LCDC/LVDS

	Port 1 -> DSI1 Cmd/Video

	Port 2 -> DSI2 Cmd/Video

	Port 3 -> DTV

Optional properties:

- gpus: phandle for gpu device

- clock-names: the following clocks are optional:

  * "lut_clk"

/ {

	...

	mdp: qcom,mdp@5100000 {

	hdmi: hdmi@4a00000 {

		...

		ports {

			...

			port@0 {

				reg = <0>;

				hdmi_in: endpoint {

					remote-endpoint = <&mdp_dtv_out>;

				};

			};

			...

		};

		...

	};

	...

	mdp: mdp@5100000 {

		compatible = "qcom,mdp4";

		reg = <0x05100000 0xf0000>;

		interrupts = <GIC_SPI 75 0>;

		connectors = <&hdmi>;

		gpus = <&gpu>;

		clock-names =

		    "core_clk",

		    "iface_clk",

		    "lut_clk",

		    "src_clk",

		    "hdmi_clk",

		    "mdp_clk";

		    "tv_clk";

		clocks =

		    <&mmcc MDP_SRC>,

		    <&mmcc MDP_CLK>,

		    <&mmcc MDP_AHB_CLK>,

		    <&mmcc MDP_AXI_CLK>,

		    <&mmcc MDP_LUT_CLK>,

		    <&mmcc TV_SRC>,

		    <&mmcc HDMI_TV_CLK>,

		    <&mmcc MDP_TV_CLK>;

		ports {

			#address-cells = <1>;

			#size-cells = <0>;

				port@0 {

					reg = <0>;

					mdp_lvds_out: endpoint {

					};

				};

				port@1 {

					reg = <1>;

					mdp_dsi1_out: endpoint {

					};

				};

				port@2 {

					reg = <2>;

					mdp_dsi2_out: endpoint {

					};

				};

				port@3 {

					reg = <3>;

					mdp_dtv_out: endpoint {

						remote-endpoint = <&hdmi_in>;

					};

				};

		};

	};

};

Qualcomm adreno/snapdragon MDP5 display controller

Description:

This is the bindings documentation for the Mobile Display Subsytem(MDSS) that

encapsulates sub-blocks like MDP5, DSI, HDMI, eDP etc, and the MDP5 display

controller found in SoCs like MSM8974, APQ8084, MSM8916, MSM8994 and MSM8996.

MDSS:

Required properties:

- compatible:

  * "qcom,mdss" - MDSS

- reg: Physical base address and length of the controller's registers.

- reg-names: The names of register regions. The following regions are required:

  * "mdss_phys"

  * "vbif_phys"

- interrupts: The interrupt signal from MDSS.

- interrupt-controller: identifies the node as an interrupt controller.

- #interrupt-cells: specifies the number of cells needed to encode an interrupt

  source, should be 1.

- power-domains: a power domain consumer specifier according to

  Documentation/devicetree/bindings/power/power_domain.txt

- clocks: device clocks. See ../clocks/clock-bindings.txt for details.

- clock-names: the following clocks are required.

  * "iface_clk"

  * "bus_clk"

  * "vsync_clk"

- #address-cells: number of address cells for the MDSS children. Should be 1.

- #size-cells: Should be 1.

- ranges: parent bus address space is the same as the child bus address space.

Optional properties:

- clock-names: the following clocks are optional:

  * "lut_clk"

MDP5:

Required properties:

- compatible:

  * "qcom,mdp5" - MDP5

- reg: Physical base address and length of the controller's registers.

- reg-names: The names of register regions. The following regions are required:

  * "mdp_phys"

- interrupts: Interrupt line from MDP5 to MDSS interrupt controller.

- interrupt-parent: phandle to the MDSS block

  through MDP block

- clocks: device clocks. See ../clocks/clock-bindings.txt for details.

- clock-names: the following clocks are required.

-   * "bus_clk"

-   * "iface_clk"

-   * "core_clk"

-   * "vsync_clk"

- ports: contains the list of output ports from MDP. These connect to interfaces

  that are external to the MDP hardware, such as HDMI, DSI, EDP etc (LVDS is a

  special case since it is a part of the MDP block itself).

  Each output port contains an endpoint that describes how it is connected to an

  external interface. These are described by the standard properties documented

  here:

	Documentation/devicetree/bindings/graph.txt

	Documentation/devicetree/bindings/media/video-interfaces.txt

  The availability of output ports can vary across SoC revisions:

  For MSM8974 and APQ8084:

	 Port 0 -> MDP_INTF0 (eDP)

	 Port 1 -> MDP_INTF1 (DSI1)

	 Port 2 -> MDP_INTF2 (DSI2)

	 Port 3 -> MDP_INTF3 (HDMI)

  For MSM8916:

	 Port 0 -> MDP_INTF1 (DSI1)

  For MSM8994 and MSM8996:

	 Port 0 -> MDP_INTF1 (DSI1)

	 Port 1 -> MDP_INTF2 (DSI2)

	 Port 2 -> MDP_INTF3 (HDMI)

Optional properties:

- clock-names: the following clocks are optional:

  * "lut_clk"

Example:

/ {

	...

	mdss: mdss@1a00000 {

		compatible = "qcom,mdss";

		reg = <0x1a00000 0x1000>,

		      <0x1ac8000 0x3000>;

		reg-names = "mdss_phys", "vbif_phys";

		power-domains = <&gcc MDSS_GDSC>;

		clocks = <&gcc GCC_MDSS_AHB_CLK>,

			 <&gcc GCC_MDSS_AXI_CLK>,

			 <&gcc GCC_MDSS_VSYNC_CLK>;

		clock-names = "iface_clk",

			      "bus_clk",

			      "vsync_clk"

		interrupts = <0 72 0>;

		interrupt-controller;

		#interrupt-cells = <1>;

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;

		mdp: mdp@1a01000 {

			compatible = "qcom,mdp5";

			reg = <0x1a01000 0x90000>;

			reg-names = "mdp_phys";

			interrupt-parent = <&mdss>;

			interrupts = <0 0>;

			clocks = <&gcc GCC_MDSS_AHB_CLK>,

				 <&gcc GCC_MDSS_AXI_CLK>,

				 <&gcc GCC_MDSS_MDP_CLK>,

				 <&gcc GCC_MDSS_VSYNC_CLK>;

			clock-names = "iface_clk",

				      "bus_clk",

				      "core_clk",

				      "vsync_clk";

			ports {

				#address-cells = <1>;

				#size-cells = <0>;

				port@0 {

					reg = <0>;

					mdp5_intf1_out: endpoint {

						remote-endpoint = <&dsi0_in>;

					};

				};

			};

		};

		dsi0: dsi@1a98000 {

			...

			ports {

				...

				port@0 {

					reg = <0>;

					dsi0_in: endpoint {

						remote-endpoint = <&mdp5_intf1_out>;

					};

				};

				...

			};

			...

		};

		dsi_phy0: dsi-phy@1a98300 {

			...

		};

	};

};

	select SHMEM

	select TMPFS

	select QCOM_SCM

	select SND_SOC_HDMI_CODEC if SND_SOC

	default y

	help

	  DRM/KMS driver for MSM/snapdragon.

	mdp/mdp5/mdp5_crtc.o \

	mdp/mdp5/mdp5_encoder.o \

	mdp/mdp5/mdp5_irq.o \

	mdp/mdp5/mdp5_mdss.o \

	mdp/mdp5/mdp5_kms.o \

	mdp/mdp5/mdp5_plane.o \

	mdp/mdp5/mdp5_smp.o \

	msm_fence.o \

	msm_gem.o \

	msm_gem_prime.o \

	msm_gem_shrinker.o \

	msm_gem_submit.o \

	msm_gpu.o \

	msm_iommu.o \