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Commit d2d05c65 authored by Tony Lindgren's avatar Tony Lindgren Committed by Linus Walleij
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gpio: omap: Fix regression for MPUIO interrupts 



At some point with all the GPIO clean-up we've broken the
MPUIO interrupts. Those are just a little bit different from
the GPIO interrupts, so we can fix it up just by setting
different irqchip functions for it. And then we can just
remove all old code trying to do the same.

Cc: Aaro Koskinen <aaro.koskinen@iki.fi>
Cc: Javier Martinez Canillas <javier@dowhile0.org>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Nishanth Menon <nm@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
Reviewed-by: default avatarGrygorii Strashko <grygorii.strashko@linaro.org>
Acked-by: default avatarSantosh Shilimkar <ssantosh@kernel.org>
Reviewed-by: default avatarFelipe Balbi <balbi@ti.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 483d8211

drivers/gpio/gpio-omap.c

+9 −39
Original line number Diff line number Diff line
@@ -1054,38 +1054,8 @@ static void omap_gpio_mod_init(struct gpio_bank *bank) 
		dev_err(bank->dev, "Could not get gpio dbck\n");

}



static void

omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start,

		    unsigned int num)

{

	struct irq_chip_generic *gc;

	struct irq_chip_type *ct;



	gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base,

				    handle_simple_irq);

	if (!gc) {

		dev_err(bank->dev, "Memory alloc failed for gc\n");

		return;

	}



	ct = gc->chip_types;



	/* NOTE: No ack required, reading IRQ status clears it. */

	ct->chip.irq_mask = irq_gc_mask_set_bit;

	ct->chip.irq_unmask = irq_gc_mask_clr_bit;

	ct->chip.irq_set_type = omap_gpio_irq_type;



	if (bank->regs->wkup_en)

		ct->chip.irq_set_wake = omap_gpio_wake_enable;



	ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride;

	irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,

			       IRQ_NOREQUEST | IRQ_NOPROBE, 0);

}



static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc)

{

	int j;

	static int gpio;

	int irq_base = 0;

	int ret;
@@ -1132,6 +1102,15 @@ static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc) 
	}

#endif



	/* MPUIO is a bit different, reading IRQ status clears it */

	if (bank->is_mpuio) {

		irqc->irq_ack = dummy_irq_chip.irq_ack;

		irqc->irq_mask = irq_gc_mask_set_bit;

		irqc->irq_unmask = irq_gc_mask_clr_bit;

		if (!bank->regs->wkup_en)

			irqc->irq_set_wake = NULL;

	}



	ret = gpiochip_irqchip_add(&bank->chip, irqc,

				   irq_base, omap_gpio_irq_handler,

				   IRQ_TYPE_NONE);
@@ -1145,15 +1124,6 @@ static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc) 
	gpiochip_set_chained_irqchip(&bank->chip, irqc,

				     bank->irq, omap_gpio_irq_handler);



	for (j = 0; j < bank->width; j++) {

		int irq = irq_find_mapping(bank->chip.irqdomain, j);

		if (bank->is_mpuio) {

			omap_mpuio_alloc_gc(bank, irq, bank->width);

			irq_set_chip_and_handler(irq, NULL, NULL);

			set_irq_flags(irq, 0);

		}

	}



	return 0;

}