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Commit d24bb3e5 authored by Andrzej Hajda's avatar Andrzej Hajda Committed by Inki Dae
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drm/exynos/hdmi: improve HDMI/ACR related code 



Simple formula can be used to calculate CTS and N coefficients.
Additionaly ACR registers have different offsets for different versions
of IP.

Signed-off-by: default avatarAndrzej Hajda <a.hajda@samsung.com>
Signed-off-by: default avatarInki Dae <inki.dae@samsung.com>
parent 185f22d2

drivers/gpu/drm/exynos/exynos_hdmi.c

+13 −58
Original line number Diff line number Diff line
@@ -71,12 +71,18 @@ enum hdmi_mapped_regs { 
	HDMI_PHY_STATUS = HDMI_MAPPED_BASE,

	HDMI_PHY_RSTOUT,

	HDMI_ACR_CON,

	HDMI_ACR_MCTS0,

	HDMI_ACR_CTS0,

	HDMI_ACR_N0

};



static const u32 hdmi_reg_map[][HDMI_TYPE_COUNT] = {

	{ HDMI_V13_PHY_STATUS, HDMI_PHY_STATUS_0 },

	{ HDMI_V13_PHY_RSTOUT, HDMI_V14_PHY_RSTOUT },

	{ HDMI_V13_ACR_CON, HDMI_V14_ACR_CON },

	{ HDMI_V13_ACR_MCTS0, HDMI_V14_ACR_MCTS0 },

	{ HDMI_V13_ACR_CTS0, HDMI_V14_ACR_CTS0 },

	{ HDMI_V13_ACR_N0, HDMI_V14_ACR_N0 },

};



static const char * const supply[] = {
@@ -1106,65 +1112,16 @@ static bool hdmi_mode_fixup(struct drm_encoder *encoder, 
	return true;

}



static void hdmi_set_acr(u32 freq, u8 *acr)

static void hdmi_reg_acr(struct hdmi_context *hdata, u32 freq)

{

	u32 n, cts;



	switch (freq) {

	case 32000:

		n = 4096;

		cts = 27000;

		break;

	case 44100:

		n = 6272;

		cts = 30000;

		break;

	case 88200:

		n = 12544;

		cts = 30000;

		break;

	case 176400:

		n = 25088;

		cts = 30000;

		break;

	case 48000:

		n = 6144;

		cts = 27000;

		break;

	case 96000:

		n = 12288;

		cts = 27000;

		break;

	case 192000:

		n = 24576;

		cts = 27000;

		break;

	default:

		n = 0;

		cts = 0;

		break;

	}



	acr[1] = cts >> 16;

	acr[2] = cts >> 8 & 0xff;

	acr[3] = cts & 0xff;

	cts = (freq % 9) ? 27000 : 30000;

	n = 128 * freq / (27000000 / cts);



	acr[4] = n >> 16;

	acr[5] = n >> 8 & 0xff;

	acr[6] = n & 0xff;

}



static void hdmi_reg_acr(struct hdmi_context *hdata, u8 *acr)

{

	hdmi_reg_writeb(hdata, HDMI_ACR_N0, acr[6]);

	hdmi_reg_writeb(hdata, HDMI_ACR_N1, acr[5]);

	hdmi_reg_writeb(hdata, HDMI_ACR_N2, acr[4]);

	hdmi_reg_writeb(hdata, HDMI_ACR_MCTS0, acr[3]);

	hdmi_reg_writeb(hdata, HDMI_ACR_MCTS1, acr[2]);

	hdmi_reg_writeb(hdata, HDMI_ACR_MCTS2, acr[1]);

	hdmi_reg_writeb(hdata, HDMI_ACR_CTS0, acr[3]);

	hdmi_reg_writeb(hdata, HDMI_ACR_CTS1, acr[2]);

	hdmi_reg_writeb(hdata, HDMI_ACR_CTS2, acr[1]);

	hdmi_reg_writev(hdata, HDMI_ACR_N0, 3, n);

	hdmi_reg_writev(hdata, HDMI_ACR_MCTS0, 3, cts);

	hdmi_reg_writev(hdata, HDMI_ACR_CTS0, 3, cts);

	hdmi_reg_writeb(hdata, HDMI_ACR_CON, 4);

}
@@ -1173,7 +1130,6 @@ static void hdmi_audio_init(struct hdmi_context *hdata) 
	u32 sample_rate, bits_per_sample;

	u32 data_num, bit_ch, sample_frq;

	u32 val;

	u8 acr[7];



	sample_rate = 44100;

	bits_per_sample = 16;
@@ -1193,8 +1149,7 @@ static void hdmi_audio_init(struct hdmi_context *hdata) 
		break;

	}



	hdmi_set_acr(sample_rate, acr);

	hdmi_reg_acr(hdata, acr);

	hdmi_reg_acr(hdata, sample_rate);



	hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CON, HDMI_I2S_IN_DISABLE

				| HDMI_I2S_AUD_I2S | HDMI_I2S_CUV_I2S_ENABLE

drivers/gpu/drm/exynos/regs-hdmi.h

+19 −10
Original line number Diff line number Diff line
@@ -72,7 +72,6 @@ 
#define HDMI_V13_V_SYNC_GEN_3_0		HDMI_CORE_BASE(0x0150)

#define HDMI_V13_V_SYNC_GEN_3_1		HDMI_CORE_BASE(0x0154)

#define HDMI_V13_V_SYNC_GEN_3_2		HDMI_CORE_BASE(0x0158)

#define HDMI_V13_ACR_CON		HDMI_CORE_BASE(0x0180)

#define HDMI_V13_AVI_CON		HDMI_CORE_BASE(0x0300)

#define HDMI_V13_AVI_BYTE(n)		HDMI_CORE_BASE(0x0320 + 4 * (n))

#define HDMI_V13_DC_CONTROL		HDMI_CORE_BASE(0x05C0)
@@ -277,16 +276,26 @@ 
#define HDMI_ASP_CHCFG2			HDMI_CORE_BASE(0x0318)

#define HDMI_ASP_CHCFG3			HDMI_CORE_BASE(0x031C)



#define HDMI_V13_ACR_CON		HDMI_CORE_BASE(0x0180)

#define HDMI_V13_ACR_MCTS0		HDMI_CORE_BASE(0x0184)

#define HDMI_V13_ACR_MCTS1		HDMI_CORE_BASE(0x0188)

#define HDMI_V13_ACR_MCTS2		HDMI_CORE_BASE(0x018C)

#define HDMI_V13_ACR_CTS0		HDMI_CORE_BASE(0x0190)

#define HDMI_V13_ACR_CTS1		HDMI_CORE_BASE(0x0194)

#define HDMI_V13_ACR_CTS2		HDMI_CORE_BASE(0x0198)

#define HDMI_V13_ACR_N0			HDMI_CORE_BASE(0x01A0)

#define HDMI_V13_ACR_N1			HDMI_CORE_BASE(0x01A4)

#define HDMI_V13_ACR_N2			HDMI_CORE_BASE(0x01A8)

#define HDMI_V14_ACR_CON		HDMI_CORE_BASE(0x0400)

#define HDMI_ACR_MCTS0			HDMI_CORE_BASE(0x0410)

#define HDMI_ACR_MCTS1			HDMI_CORE_BASE(0x0414)

#define HDMI_ACR_MCTS2			HDMI_CORE_BASE(0x0418)

#define HDMI_ACR_CTS0			HDMI_CORE_BASE(0x0420)

#define HDMI_ACR_CTS1			HDMI_CORE_BASE(0x0424)

#define HDMI_ACR_CTS2			HDMI_CORE_BASE(0x0428)

#define HDMI_ACR_N0			HDMI_CORE_BASE(0x0430)

#define HDMI_ACR_N1			HDMI_CORE_BASE(0x0434)

#define HDMI_ACR_N2			HDMI_CORE_BASE(0x0438)

#define HDMI_V14_ACR_MCTS0		HDMI_CORE_BASE(0x0410)

#define HDMI_V14_ACR_MCTS1		HDMI_CORE_BASE(0x0414)

#define HDMI_V14_ACR_MCTS2		HDMI_CORE_BASE(0x0418)

#define HDMI_V14_ACR_CTS0		HDMI_CORE_BASE(0x0420)

#define HDMI_V14_ACR_CTS1		HDMI_CORE_BASE(0x0424)

#define HDMI_V14_ACR_CTS2		HDMI_CORE_BASE(0x0428)

#define HDMI_V14_ACR_N0			HDMI_CORE_BASE(0x0430)

#define HDMI_V14_ACR_N1			HDMI_CORE_BASE(0x0434)

#define HDMI_V14_ACR_N2			HDMI_CORE_BASE(0x0438)



/* Packet related registers */

#define HDMI_ACP_CON			HDMI_CORE_BASE(0x0500)