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Unverified Commit d230856d authored by Michael Bestas's avatar Michael Bestas
Browse files

Merge tag 'LA.UM.9.12.r1-15100-SMxx50.QSSI13.0' of... 

Merge tag 'LA.UM.9.12.r1-15100-SMxx50.QSSI13.0' of https://git.codelinaro.org/clo/la/platform/vendor/opensource/display-drivers into android13-4.19-kona

"LA.UM.9.12.r1-15100-SMxx50.QSSI13.0"

* tag 'LA.UM.9.12.r1-15100-SMxx50.QSSI13.0' of https://git.codelinaro.org/clo/la/platform/vendor/opensource/display-drivers:
  disp: msm: dp: disable ASSR before link training
  disp: msm: dsi: clear the panel esd_recovery_pending in power on commit

Change-Id: I3452dbc689d042edee94b74b7e85e320a996064d
parents 80d310ce 7751ac5a

techpack/display/msm/dp/dp_catalog.c

+7 −1
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.

 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.

 */
@@ -986,7 +987,12 @@ static void dp_catalog_ctrl_config_ctrl(struct dp_catalog_ctrl *ctrl, u8 ln_cnt) 
	io_data = catalog->io.dp_link;



	cfg = dp_read(DP_CONFIGURATION_CTRL);

	cfg &= ~(BIT(4) | BIT(5));

	/*

	 * Reset ASSR (alternate scrambler seed reset) by resetting BIT(10).

	 * ASSR should be set to disable for TPS4 link training pattern.

	 * Forcing it to 0 as the power on reset value of register enables it.

	 */

	cfg &= ~(BIT(4) | BIT(5) | BIT(10));

	cfg |= (ln_cnt - 1) << 4;

	dp_write(DP_CONFIGURATION_CTRL, cfg);

techpack/display/msm/dsi/dsi_drm.c

+2 −1
Original line number Diff line number Diff line
@@ -176,6 +176,7 @@ static void dsi_bridge_pre_enable(struct drm_bridge *bridge) 
		return;

	}



	if (bridge->encoder->crtc->state->active_changed)

		atomic_set(&c_bridge->display->panel->esd_recovery_pending, 0);



	/* By this point mode should have been validated through mode_fixup */