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Commit d1c3f311 authored by Elson Roy Serrao's avatar Elson Roy Serrao
Browse files

ARM: dts: msm: Update the QMP PHY init Sequence for Kona 

Update the QMP PHY init Sequence as per the HPG Rev1.03
settings.

Change-Id: I5eab834a66a9074d20ddc7cd69c4b9d83a01f5e9
parent 0136ddaf

qcom/kona-usb.dtsi

+14 −10
Original line number Diff line number Diff line
@@ -204,18 +204,20 @@ 
			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x11 0

			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x02 0

			USB3_DP_QSERDES_TXA_LANE_MODE_1 0xD5 0

			USB3_DP_QSERDES_TXA_LANE_MODE_2 0x00 0

			USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12 0

			USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x40 0

			USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x06 0

			USB3_DP_QSERDES_RXA_UCDR_FO_GAIN 0x09 0

			USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x05 0

			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x2F 0

			USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0

			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0xFF 0

			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0

			USB3_DP_QSERDES_RXA_UCDR_PI_CONTROLS 0x99 0

			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH1 0x04 0

			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH1 0x08 0

			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH2 0x08 0

			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1 0x05 0

			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2 0x05 0

			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1 0x00 0

			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2 0x04 0

			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x54 0

			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x0C 0

			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x0F 0
@@ -247,18 +249,20 @@ 
			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x11 0

			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x02 0

			USB3_DP_QSERDES_TXB_LANE_MODE_1 0xD5 0

			USB3_DP_QSERDES_TXB_LANE_MODE_2 0x00 0

			USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12 0

			USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x54 0

			USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x06 0

			USB3_DP_QSERDES_RXB_UCDR_FO_GAIN 0x09 0

			USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x05 0

			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x2F 0

			USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0

			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0xFF 0

			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0

			USB3_DP_QSERDES_RXB_UCDR_PI_CONTROLS 0x99 0

			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH1 0x04 0

			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH1 0x08 0

			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH2 0x08 0

			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1 0x05 0

			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2 0x05 0

			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1 0x00 0

			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2 0x04 0

			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x54 0

			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x0C 0

			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x0F 0
@@ -271,9 +275,9 @@ 
			USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0E 0

			USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0x7F 0

			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0xFF 0

			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0x7F 0

			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0x3F 0

			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0x7F 0

			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0x97 0

			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0xA6 0

			USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0xDC 0

			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0xDC 0

			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0x5C 0