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Commit d19bb397 authored by Tomasz Figa's avatar Tomasz Figa
Browse files

ARM: dts: exynos: Update PMU node with CLKOUT related data 



This patch extends nodes of PMU system controller on Exynos4210, 4x12,
5250 and 5420 SoCs with newly defined properties used by Exynos CLKOUT
driver.

Signed-off-by: default avatarTomasz Figa <t.figa@samsung.com>
parent 1e832e51

arch/arm/boot/dts/exynos4210.dtsi

+10 −0
Original line number Diff line number Diff line
@@ -31,6 +31,16 @@ 
		pinctrl2 = &pinctrl_2;

	};



	pmu_system_controller: system-controller@10020000 {

		clock-names = "clkout0", "clkout1", "clkout2", "clkout3",

				"clkout4", "clkout8", "clkout9";

		clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,

			<&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,

			<&clock CLK_OUT_CPU>, <&clock CLK_XXTI>,

			<&clock CLK_XUSBXTI>;

		#clock-cells = <1>;

	};



	sysram@02020000 {

		compatible = "mmio-sram";

		reg = <0x02020000 0x20000>;

arch/arm/boot/dts/exynos4x12.dtsi

+7 −0
Original line number Diff line number Diff line
@@ -139,6 +139,13 @@ 


	pmu_system_controller: system-controller@10020000 {

		compatible = "samsung,exynos4212-pmu", "syscon";

		clock-names = "clkout0", "clkout1", "clkout2", "clkout3",

				"clkout4", "clkout8", "clkout9";

		clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,

			<&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,

			<&clock CLK_OUT_CPU>, <&clock CLK_XXTI>,

			<&clock CLK_XUSBXTI>;

		#clock-cells = <1>;

	};



	g2d@10800000 {

arch/arm/boot/dts/exynos5250.dtsi

+3 −0
Original line number Diff line number Diff line
@@ -191,6 +191,9 @@ 
	pmu_system_controller: system-controller@10040000 {

		compatible = "samsung,exynos5250-pmu", "syscon";

		reg = <0x10040000 0x5000>;

		clock-names = "clkout16";

		clocks = <&clock CLK_FIN_PLL>;

		#clock-cells = <1>;

	};



	sysreg_system_controller: syscon@10050000 {

arch/arm/boot/dts/exynos5420.dtsi

+3 −0
Original line number Diff line number Diff line
@@ -724,6 +724,9 @@ 
	pmu_system_controller: system-controller@10040000 {

		compatible = "samsung,exynos5420-pmu", "syscon";

		reg = <0x10040000 0x5000>;

		clock-names = "clkout16";

		clocks = <&clock CLK_FIN_PLL>;

		#clock-cells = <1>;

	};



	sysreg_system_controller: syscon@10050000 {