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Commit d16605c9 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'pinctrl-v4.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl 

Pull pin control updates from Linus Walleij:
 "This is the big bulk of pin control changes for the v4.14 kernel.
  There are just a few bigger changes (new drivers mostly) and then a
  lot of small patches all over the place.

  Core changes:
   - Decision to wrap the sleep mode of the Spreadtrum and in the future
     others into a specially tagged state. The generic DT bindings and
     the new Spreadtrum driver conforms to this. Others should be moved
     over if possible.

  New drivers:
   - Spreadtrum SoCs especially the SC9860 SoC.
   - Storlink/Cortina Gemini 3512 and 3516 SoCs.

  New subdrivers:
   - Intel Denverton subdriver.
   - Intel Cannon Lake subdriver.
   - Intel Lewisburg subdriver.
   - Allwinner sunxi: R40 subdriver for A10.
   - Socionext uniphier PXs3 subdriver.
   - Rockchip RK3128 subdriver.
   - Renesas SH-PFC R8A77995 subdriver.

  Miscellaneous:
   - Qualcomm APQ8064 can handle general purpose clock muxing.
   - Mediatek MT7623 PCIe mux data fixed up.
   - Intel GPIO IRQs are disabled during suspend.
   - Several fixes and addtions to Renesas r8a7796.
   - Qualcomm SPMI GPIO supports dtest route and LV/MV subtype.
   - Input schmitt trigger support in Rockchip RV1108.
   - Aspeed G4 and G5 USB host/device pin control control added.
   - Qualcomm IPQ4019 has matured with a few missing pin groups and
     control bits put in place.
   - Lots of constification, this is the latest in cocinelle fixes"

* tag 'pinctrl-v4.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (147 commits)
  Revert "pinctrl: sunxi: Don't enforce bias disable (for now)"
  pinctrl: uniphier: fix members of rmii group for Pro4
  pinctrl: Delete an error message
  pinctrl: core: Delete an error message
  pinctrl: intel: Read back TX buffer state
  pinctrl: rockchip: Add rv1108 recalculated iomux support
  pinctrl: intel: Decrease indentation in intel_gpio_set()
  pinctrl: rza1: Remove suffix from gpiochip label
  pinctrl: qcom: spmi-gpio: Correct power_source range check
  pinctrl: freescale: make mxs_regs const
  pinctrl: aspeed: Rework strap register write logic for the AST2500
  pinctrl: rza1: off by one in rza1_parse_gpiochip()
  pinctrl: qcom: General Purpose clocks for apq8064
  pinctrl: sprd: Add Spreadtrum pin control driver
  dt-bindings: pinctrl: Add DT bindings for Spreadtrum SC9860
  pinctrl: Add sleep related state to indicate sleep related configs
  pinctrl: mediatek: update PCIe mux data for MT7623
  pinctrl: intel: Add Intel Lewisburg GPIO support
  pinctrl: intel: Add Intel Cannon Lake PCH-H pin controller support
  pinctrl: aspeed: Fix ast2500 strap register write logic
  ...
parents fe9e3138 ac059e2a

Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt

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Cortina Systems Gemini pin controller



This pin controller is found in the Cortina Systems Gemini SoC family,

see further arm/gemini.txt. It is a purely group-based multiplexing pin

controller.



The pin controller node must be a subnode of the system controller node.



Required properties:

- compatible: "cortina,gemini-pinctrl"



Subnodes of the pin controller contain pin control multiplexing set-up.

Please refer to pinctrl-bindings.txt for generic pin multiplexing nodes.



Example:





syscon {

	compatible = "cortina,gemini-syscon";

	...

	pinctrl {

		compatible = "cortina,gemini-pinctrl";

		pinctrl-names = "default";

		pinctrl-0 = <&dram_default_pins>, <&system_default_pins>,

		    <&vcontrol_default_pins>;



		dram_default_pins: pinctrl-dram {

			mux {

				function = "dram";

				groups = "dramgrp";

			};

		};

		rtc_default_pins: pinctrl-rtc {

			mux {

				function = "rtc";

				groups = "rtcgrp";

			};

		};

		power_default_pins: pinctrl-power {

			mux {

				function = "power";

				groups = "powergrp";

			};

		};

		system_default_pins: pinctrl-system {

			mux {

				function = "system";

				groups = "systemgrp";

			};

		};

		(...)

		uart_default_pins: pinctrl-uart {

			mux {

				function = "uart";

				groups = "uartrxtxgrp";

			};

		};

	};

};

Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt

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* Freescale i.MX7ULP IOMUX Controller



i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7

ports and IOMUXC DDR for DDR interface.



Note:

This binding doc is only for the IOMUXC1 support in A7 Domain and it only

supports generic pin config.



Please also refer pinctrl-bindings.txt in this directory for generic pinctrl

binding.



=== Pin Controller Node ===



Required properties:

- compatible:	"fsl,imx7ulp-iomuxc1"

- reg:		Should contain the base physical address and size of the iomuxc

		registers.



=== Pin Configuration Node ===

- pinmux: One integers array, represents a group of pins mux setting.

	The format is pinmux = <PIN_FUNC_ID>, PIN_FUNC_ID is a pin working on

	a specific function.



	NOTE: i.MX7ULP PIN_FUNC_ID consists of 4 integers as it shares one mux

	and config register as follows:

	<mux_conf_reg input_reg mux_mode input_val>



	Refer to imx7ulp-pinfunc.h in in device tree source folder for all

	available imx7ulp PIN_FUNC_ID.



Optional Properties:

- drive-strength		Integer. Controls Drive Strength

					0: Standard

					1: Hi Driver

- drive-push-pull		Bool. Enable Pin Push-pull

- drive-open-drain		Bool. Enable Pin Open-drian

- slew-rate:			Integer. Controls Slew Rate

					0: Standard

					1: Slow

- bias-disable:			Bool. Pull disabled

- bias-pull-down:		Bool. Pull down on pin

- bias-pull-up:			Bool. Pull up on pin



Examples:

#include "imx7ulp-pinfunc.h"



/* Pin Controller Node */

iomuxc1: iomuxc@40ac0000 {

	compatible = "fsl,imx7ulp-iomuxc1";

	reg = <0x40ac0000 0x1000>;



	/* Pin Configuration Node */

	pinctrl_lpuart4: lpuart4grp {

		pinmux = <

			IMX7ULP_PAD_PTC3__LPUART4_RX

			IMX7ULP_PAD_PTC2__LPUART4_TX

		>;

		bias-pull-up;

	};

};

Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt

+5 −3
Original line number Diff line number Diff line
@@ -69,8 +69,9 @@ PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 RGMII1 RGMII2 RMII1 RMII2 ROM16 ROM8 ROMCS1 
ROMCS2 ROMCS3 ROMCS4 RXD1 RXD2 RXD3 RXD4 SALT1 SALT2 SALT3 SALT4 SD1 SD2 SGPMCK

SGPMI SGPMLD SGPMO SGPSCK SGPSI0 SGPSI1 SGPSLD SIOONCTRL SIOPBI SIOPBO SIOPWREQ

SIOPWRGD SIOS3 SIOS5 SIOSCI SPI1 SPI1DEBUG SPI1PASSTHRU SPICS1 TIMER3 TIMER4

TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2 TXD3 TXD4 UART6 USBCKI VGABIOS_ROM VGAHS

VGAVS VPI18 VPI24 VPI30 VPO12 VPO24 WDTRST1 WDTRST2

TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2 TXD3 TXD4 UART6 USB11D1 USB11H2 USB2D1

USB2H1 USBCKI VGABIOS_ROM VGAHS VGAVS VPI18 VPI24 VPI30 VPO12 VPO24 WDTRST1

WDTRST2



aspeed,ast2500-pinctrl, aspeed,g5-pinctrl:
@@ -86,7 +87,8 @@ SALT11 SALT12 SALT13 SALT14 SALT2 SALT3 SALT4 SALT5 SALT6 SALT7 SALT8 SALT9 
SCL1 SCL2 SD1 SD2 SDA1 SDA2 SGPS1 SGPS2 SIOONCTRL SIOPBI SIOPBO SIOPWREQ

SIOPWRGD SIOS3 SIOS5 SIOSCI SPI1 SPI1CS1 SPI1DEBUG SPI1PASSTHRU SPI2CK SPI2CS0

SPI2CS1 SPI2MISO SPI2MOSI TIMER3 TIMER4 TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2

TXD3 TXD4 UART6 USBCKI VGABIOSROM VGAHS VGAVS VPI24 VPO WDTRST1 WDTRST2

TXD3 TXD4 UART6 USB11BHID USB2AD USB2AH USB2BD USB2BH USBCKI VGABIOSROM VGAHS

VGAVS VPI24 VPO WDTRST1 WDTRST2



Examples

========

Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt

+2 −0
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@@ -268,6 +268,8 @@ output-enable - enable output on a pin without actively driving it 
			  (such as enabling an output buffer)

output-low		- set the pin to output mode with low level

output-high		- set the pin to output mode with high level

sleep-hardware-state	- indicate this is sleep related state which will be programmed

			  into the registers for the sleep state.

slew-rate		- set the slew rate



For example:

Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt

+1 −0
Original line number Diff line number Diff line
@@ -5,6 +5,7 @@ The Mediatek's Pin controller is used to control SoC pins. 
Required properties:

- compatible: value should be one of the following.

	"mediatek,mt2701-pinctrl", compatible with mt2701 pinctrl.

	"mediatek,mt2712-pinctrl", compatible with mt2712 pinctrl.

	"mediatek,mt6397-pinctrl", compatible with mt6397 pinctrl.

	"mediatek,mt7623-pinctrl", compatible with mt7623 pinctrl.

	"mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl.