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Commit d14766d6 authored by Udipto Goswami's avatar Udipto Goswami Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Add HS & SS phy nodes for Khaje 

Add hs & ss phy nodes along with clock settings for
usb controller on KHAJE.

Change-Id: I832cc75f2ac7cf436e1b9765bf6494b7c1d3f269
parent 017cfa7e

qcom/khaje-usb.dtsi

+215 −1
Original line number Diff line number Diff line 
#include <dt-bindings/clock/qcom,gcc-khaje.h>

#include <dt-bindings/msm/msm-bus-ids.h>

#include <dt-bindings/phy/qcom,khaje-qmp-usb3.h>

&soc {

	/* Primary USB port related controller */

	usb0: ssusb@4e00000 {
@@ -32,6 +33,7 @@ 
		reset-names = "core_reset";



		USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>;

		dpdm-supply = <&usb2_phy0>;



		qcom,core-clk-rate = <133333333>;

		qcom,core-clk-rate-hs = <66666667>;
@@ -79,7 +81,7 @@ 
			reg = <0x4e00000 0xe000>;

			interrupt-parent = <&intc>;

			interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;

			usb-phy = <&usb_nop_phy>;

			usb-phy = <&usb2_phy0>, <&usb_qmp_dp_phy>;

			tx-fifo-resize;

			linux,sysdev_is_parent;

			snps,disable-clk-gating;
@@ -121,6 +123,218 @@ 
		};

	};



	/* Primary USB port related High Speed PHY */

	usb2_phy0: hsphy@1613000 {

		compatible = "qcom,usb-hsphy-snps-femto";

		reg = <0x1613000 0x110>,

			<0x1612000 0x4>;

		reg-names = "hsusb_phy_base",

			"eud_enable_reg";



		vdd-supply = <&L4A>;

		vdda18-supply = <&L12A>;

		vdda33-supply = <&L15A>;

		qcom,vdd-voltage-level = <0 880000 880000>;



		clocks = <&rpmcc CXO_SMD_OTG_CLK>;

		clock-names =  "ref_clk_src";



		resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;

		reset-names = "phy_reset";

		qcom,param-override-seq = <0x61 0x6c>, //override_x0

					  <0x43 0x70>, //override_x1

					  <0x2E 0x74>; //override_x2

	};



	/* Primary USB port related QMP USB PHY */

	usb_qmp_dp_phy: ssphy@1615000 {

		compatible = "qcom,usb-ssphy-qmp-dp-combo";

		reg = <0x01615000 0x3000>;

		reg-names = "qmp_phy_base";



		core-supply = <&L18A>;

		qcom,vdd-voltage-level = <0 880000 880000>;



		clocks = <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,

			 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,

			 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>,

			 <&usb3_phy_wrapper_gcc_usb30_pipe_clk>,

			 <&rpmcc CXO_SMD_OTG_CLK>,

			 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;

		clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux",

				"pipe_clk_ext_src", "ref_clk_src",

				"com_aux_clk";



		resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,

			 <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>;

		reset-names = "global_phy_reset", "phy_reset";



		qcom,qmp-phy-reg-offset =

			<USB3_DP_PCS_PCS_STATUS1

			 USB3_DP_PCS_USB3_AUTONOMOUS_MODE_CTRL

			 USB3_DP_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR

			 USB3_DP_PCS_POWER_DOWN_CONTROL

			 USB3_DP_PCS_SW_RESET

			 USB3_DP_PCS_START_CONTROL

			 0xffff /* USB3_PHY_PCS_MISC_TYPEC_CTRL */

			 0x2a18 /* USB3_DP_DP_PHY_PD_CTL */

			 USB3_DP_COM_POWER_DOWN_CTRL

			 USB3_DP_COM_SW_RESET

			 USB3_DP_COM_RESET_OVRD_CTRL

			 USB3_DP_COM_PHY_MODE_CTRL

			 USB3_DP_COM_TYPEC_CTRL

			 USB3_DP_COM_SWI_CTRL

			 USB3_DP_PCS_CLAMP_ENABLE>;



		qcom,qmp-phy-init-seq =

			/* <reg_offset, value, delay> */

			<USB3_DP_QSERDES_COM_SSC_EN_CENTER 0x01 0

			USB3_DP_QSERDES_COM_SSC_PER1 0x31 0

			USB3_DP_QSERDES_COM_SSC_PER2 0x01 0

			USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xDE 0

			USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07 0

			USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xDE 0

			USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07 0

			USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0A 0

			USB3_DP_QSERDES_COM_CMN_IPTRIM 0x20 0

			USB3_DP_QSERDES_COM_CP_CTRL_MODE0 0x06 0

			USB3_DP_QSERDES_COM_CP_CTRL_MODE1 0x06 0

			USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0

			USB3_DP_QSERDES_COM_PLL_RCTRL_MODE1 0x16 0

			USB3_DP_QSERDES_COM_PLL_CCTRL_MODE0 0x36 0

			USB3_DP_QSERDES_COM_PLL_CCTRL_MODE1 0x36 0

			USB3_DP_QSERDES_COM_SYSCLK_EN_SEL 0x1A 0

			USB3_DP_QSERDES_COM_LOCK_CMP_EN 0x04 0

			USB3_DP_QSERDES_COM_LOCK_CMP1_MODE0 0x14 0

			USB3_DP_QSERDES_COM_LOCK_CMP2_MODE0 0x34 0

			USB3_DP_QSERDES_COM_LOCK_CMP1_MODE1 0x34 0

			USB3_DP_QSERDES_COM_LOCK_CMP2_MODE1 0x82 0

			USB3_DP_QSERDES_COM_DEC_START_MODE0 0x82 0

			USB3_DP_QSERDES_COM_DEC_START_MODE1 0x82 0

			USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE0 0xAB 0

			USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE0 0xEA 0

			USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02 0

			USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE1 0xAB 0

			USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE1 0xEA 0

			USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02 0

			USB3_DP_QSERDES_COM_VCO_TUNE_MAP 0x02 0

			USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0 0x24 0

			USB3_DP_QSERDES_COM_VCO_TUNE1_MODE1 0x24 0

			USB3_DP_QSERDES_COM_VCO_TUNE2_MODE1 0x02 0

			USB3_DP_QSERDES_COM_HSCLK_SEL 0x01 0

			USB3_DP_QSERDES_COM_CORECLK_DIV_MODE1 0x08 0

			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xCA 0

			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1E 0

			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xCA 0

			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1E 0

			USB3_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11 0

			USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX 0x60 0

			USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX 0x60 0

			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x11 0

			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x02 0

			USB3_DP_QSERDES_TXA_LANE_MODE_1 0xD5 0

			USB3_DP_QSERDES_TXA_LANE_MODE_2 0x00 0

			USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12 0

			USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x40 0

			USB3_DP_QSERDES_RXA_UCDR_FO_GAIN 0x09 0

			USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x05 0

			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x2F 0

			USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0

			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0xFF 0

			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0

			USB3_DP_QSERDES_RXA_UCDR_PI_CONTROLS 0x99 0

			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH1 0x08 0

			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH2 0x08 0

			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1 0x00 0

			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2 0x04 0

			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x54 0

			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x0C 0

			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x0F 0

			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4A 0

			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x0A 0

			USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0xC0 0

			USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH 0x00 0

			USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 0

			USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x04 0

			USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x0E 0

			USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0xFF 0

			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0x7F 0

			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0x7F 0

			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0x7F 0

			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0x97 0

			USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0xDC 0

			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0xDC 0

			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0x5C 0

			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x7B 0

			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0xB4 0

			USB3_DP_QSERDES_RXA_DFE_EN_TIMER 0x04 0

			USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x38 0

			USB3_DP_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE 0xA0 0

			USB3_DP_QSERDES_RXA_DCC_CTRL1 0x0C 0

			USB3_DP_QSERDES_RXA_GM_CAL 0x1F 0

			USB3_DP_QSERDES_RXA_VTH_CODE 0x10 0

			USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX 0x60 0

			USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0x60 0

			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x11 0

			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x02 0

			USB3_DP_QSERDES_TXB_LANE_MODE_1 0xD5 0

			USB3_DP_QSERDES_TXB_LANE_MODE_2 0x00 0

			USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12 0

			USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x54 0

			USB3_DP_QSERDES_RXB_UCDR_FO_GAIN 0x09 0

			USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x05 0

			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x2F 0

			USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0

			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0xFF 0

			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0

			USB3_DP_QSERDES_RXB_UCDR_PI_CONTROLS 0x99 0

			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH1 0x08 0

			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH2 0x08 0

			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1 0x00 0

			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2 0x04 0

			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x54 0

			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x0C 0

			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x0F 0

			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4A 0

			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x0A 0

			USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0xC0 0

			USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH 0x00 0

			USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 0

			USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x04 0

			USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0E 0

			USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0x7F 0

			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0xFF 0

			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0x3F 0

			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0x7F 0

			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0xA6 0

			USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0xDC 0

			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0xDC 0

			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0x5C 0

			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x7B 0

			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0xB4 0

			USB3_DP_QSERDES_RXB_DFE_EN_TIMER 0x04 0

			USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x38 0

			USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE 0xA0 0

			USB3_DP_QSERDES_RXB_DCC_CTRL1 0x0C 0

			USB3_DP_QSERDES_RXB_GM_CAL 0x1F 0

			USB3_DP_QSERDES_RXB_VTH_CODE 0x10 0

			USB3_DP_PCS_LOCK_DETECT_CONFIG1 0xD0 0

			USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x07 0

			USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x20 0

			USB3_DP_PCS_LOCK_DETECT_CONFIG6 0x13 0

			USB3_DP_PCS_REFGEN_REQ_CONFIG1 0x21 0

			USB3_DP_PCS_RX_SIGDET_LVL 0xA9 0

			USB3_DP_PCS_CDR_RESET_TIME 0x0A 0

			USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0x88 0

			USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x13 0

			USB3_DP_PCS_PCS_TX_RX_CONFIG 0x0C 0

			USB3_DP_PCS_EQ_CONFIG1 0x4B 0

			USB3_DP_PCS_EQ_CONFIG5 0x10 0

			USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8 0

			USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0

			0xffffffff 0xffffffff 0x00>;

	};



	usb_nop_phy: usb_nop_phy {

		compatible = "usb-nop-xceiv";

	};