Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit d0e224f9 authored by Tomi Valkeinen's avatar Tomi Valkeinen
Browse files

OMAPDSS: fix rounding when calculating fclk rate 



"clk: divider: fix rate calculation for fractional rates" patch (and
similar for TI specific divider) fixes the clk-divider's rounding. This
patch updates the DSS driver to round the rates accordingly.

This fixes the DSS's warnings about clock rate mismatch, and also fixes
the wrong fclk rate being set.

Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
Tested-by: default avatarChristoph Fritz <chf.fritz@googlemail.com>
Tested-by: default avatarMarek Belisko <marek@goldelico.com>
parent 8d018647

drivers/video/omap2/dss/dss.c

+2 −2
Original line number Diff line number Diff line
@@ -457,7 +457,7 @@ bool dss_div_calc(unsigned long pck, unsigned long fck_min, 
	fckd_stop = max(DIV_ROUND_UP(prate * m, fck_hw_max), 1ul);



	for (fckd = fckd_start; fckd >= fckd_stop; --fckd) {

		fck = prate / fckd * m;

		fck = DIV_ROUND_UP(prate, fckd) * m;



		if (func(fck, data))

			return true;
@@ -506,7 +506,7 @@ static int dss_setup_default_clock(void) 


		fck_div = DIV_ROUND_UP(prate * dss.feat->dss_fck_multiplier,

				max_dss_fck);

		fck = prate / fck_div * dss.feat->dss_fck_multiplier;

		fck = DIV_ROUND_UP(prate, fck_div) * dss.feat->dss_fck_multiplier;

	}



	r = dss_set_fck_rate(fck);