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Commit d0b791c0 authored by Michael Ellerman's avatar Michael Ellerman
Browse files

powerpc/64s/idle: Consolidate power9_offline_stop()/power9_idle_stop() 



Commit 3d4fbffd ("powerpc/64s/idle: POWER9 implement a separate
idle stop function for hotplug") that added power9_offline_stop() was
written before commit 7672691a ("powerpc/powernv: Provide a way to
force a core into SMT4 mode").

When merging the former I failed to notice that it caused us to skip
the force-SMT4 logic for offline CPUs. The result is that offlined
CPUs will not correctly participate in the force-SMT4 logic, which
presumably will result in badness (not tested).

Reconcile the two commits by making power9_offline_stop() a pre-cursor
to power9_idle_stop(), so that they share the force-SMT4 logic.

This is based on an original commit from Nick, all breakage is my own.

Fixes: 3d4fbffd ("powerpc/64s/idle: POWER9 implement a separate idle stop function for hotplug")
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Signed-off-by: default avatarNicholas Piggin <npiggin@gmail.com>
parent f2748bdf

arch/powerpc/kernel/idle_book3s.S

+11 −12
Original line number Diff line number Diff line
@@ -422,25 +422,24 @@ ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_ARCH_207S, 66); \ 
/*

 * Entered with MSR[EE]=0 and no soft-masked interrupts pending.

 * r3 contains desired PSSCR register value.

 *

 * Offline (CPU unplug) case also must notify KVM that the CPU is

 * idle.

 */

_GLOBAL(power9_offline_stop)

	std	r3, PACA_REQ_PSSCR(r13)

	mtspr 	SPRN_PSSCR,r3

#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE

	/* Tell KVM we're entering idle */

	/*

	 * Tell KVM we're entering idle.

	 * This does not have to be done in real mode because the P9 MMU

	 * is independent per-thread. Some steppings share radix/hash mode

	 * between threads, but in that case KVM has a barrier sync in real

	 * mode before and after switching between radix and hash.

	 */

	li	r4,KVM_HWTHREAD_IN_IDLE

	/* DO THIS IN REAL MODE!  See comment above. */

	stb	r4,HSTATE_HWTHREAD_STATE(r13)

#endif

	LOAD_REG_ADDR(r4,power_enter_stop)

	b	pnv_powersave_common

	/* No return */

	/* fall through */





/*

 * Entered with MSR[EE]=0 and no soft-masked interrupts pending.

 * r3 contains desired PSSCR register value.

 */

_GLOBAL(power9_idle_stop)

	std	r3, PACA_REQ_PSSCR(r13)

#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE