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Commit d082852f authored by Anson Huang's avatar Anson Huang Committed by Shawn Guo
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ARM: imx: enable bus auto clock gating function for i.mx6sll 



i.MX6SLL has HW bus auto clock gating function, enable
it by default to save VDD_SOC_IN power, about 5% ~ 20%
saved depends on different use cases.

Signed-off-by: default avatarAnson Huang <Anson.Huang@nxp.com>
Acked-by: default avatarLee Jones <lee.jones@linaro.org>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 83ef5da0

arch/arm/mach-imx/pm-imx6.c

+9 −2
Original line number Diff line number Diff line
@@ -648,10 +648,17 @@ void __init imx6dl_pm_init(void) 


void __init imx6sl_pm_init(void)

{

	if (cpu_is_imx6sl())

	struct regmap *gpr;



	if (cpu_is_imx6sl()) {

		imx6_pm_common_init(&imx6sl_pm_data);

	else

	} else {

		imx6_pm_common_init(&imx6sll_pm_data);

		gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");

		if (!IS_ERR(gpr))

			regmap_update_bits(gpr, IOMUXC_GPR5,

				IMX6SLL_GPR5_AFCG_X_BYPASS_MASK, 0);

	}

}



void __init imx6sx_pm_init(void)

include/linux/mfd/syscon/imx6q-iomuxc-gpr.h

+3 −0
Original line number Diff line number Diff line
@@ -457,4 +457,7 @@ 
#define MCLK_DIR(x) (x == 1 ? IMX6UL_GPR1_SAI1_MCLK_DIR : x == 2 ? \

		     IMX6UL_GPR1_SAI2_MCLK_DIR : IMX6UL_GPR1_SAI3_MCLK_DIR)



/* For imx6sll iomux gpr register field define */

#define IMX6SLL_GPR5_AFCG_X_BYPASS_MASK		(0x1f << 11)



#endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */