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Commit d037e100 authored by Rajendra Nayak's avatar Rajendra Nayak Committed by Paul Walmsley
Browse files

ARM: OMAP2: clock: Cleanup !CONFIG_COMMON_CLK parts 



Clean all #ifdef's added to OMAP2 clock code to make it COMMON clk
ready, not that CONFIG_COMMON_CLK is enabled.

Signed-off-by: default avatarRajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: also drop CONFIG_COMMON_CLK tests around APLL recalc_rate
 functions]
Signed-off-by: default avatarMike Turquette <mturquette@ti.com>
[paul@pwsan.com: remove some ifdefs in mach-omap2/io.c]
Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
parent 455db9c9

arch/arm/mach-omap2/clkt2xxx_apll.c

+0 −52
Original line number Diff line number Diff line
@@ -38,7 +38,6 @@ 


/* Private functions */



#ifdef CONFIG_COMMON_CLK

/**

 * omap2xxx_clk_apll_locked - is the APLL locked?

 * @hw: struct clk_hw * of the APLL to check
@@ -57,81 +56,47 @@ static bool omap2xxx_clk_apll_locked(struct clk_hw *hw) 


	return ((r & apll_mask) == apll_mask) ? true : false;

}

#endif



#ifdef CONFIG_COMMON_CLK

int omap2_clk_apll96_enable(struct clk_hw *hw)

#else

static int _apll96_enable(struct clk *clk)

#endif

{

	return omap2xxx_cm_apll96_enable();

}



#ifdef CONFIG_COMMON_CLK

int omap2_clk_apll54_enable(struct clk_hw *hw)

#else

static int _apll54_enable(struct clk *clk)

#endif

{

	return omap2xxx_cm_apll54_enable();

}



#ifdef CONFIG_COMMON_CLK

static void _apll96_allow_idle(struct clk_hw_omap *clk)

#else

static void _apll96_allow_idle(struct clk *clk)

#endif

{

	omap2xxx_cm_set_apll96_auto_low_power_stop();

}



#ifdef CONFIG_COMMON_CLK

static void _apll96_deny_idle(struct clk_hw_omap *clk)

#else

static void _apll96_deny_idle(struct clk *clk)

#endif

{

	omap2xxx_cm_set_apll96_disable_autoidle();

}



#ifdef CONFIG_COMMON_CLK

static void _apll54_allow_idle(struct clk_hw_omap *clk)

#else

static void _apll54_allow_idle(struct clk *clk)

#endif

{

	omap2xxx_cm_set_apll54_auto_low_power_stop();

}



#ifdef CONFIG_COMMON_CLK

static void _apll54_deny_idle(struct clk_hw_omap *clk)

#else

static void _apll54_deny_idle(struct clk *clk)

#endif

{

	omap2xxx_cm_set_apll54_disable_autoidle();

}



#ifdef CONFIG_COMMON_CLK

void omap2_clk_apll96_disable(struct clk_hw *hw)

#else

static void _apll96_disable(struct clk *clk)

#endif

{

	omap2xxx_cm_apll96_disable();

}



#ifdef CONFIG_COMMON_CLK

void omap2_clk_apll54_disable(struct clk_hw *hw)

#else

static void _apll54_disable(struct clk *clk)

#endif

{

	omap2xxx_cm_apll54_disable();

}



#ifdef CONFIG_COMMON_CLK

unsigned long omap2_clk_apll54_recalc(struct clk_hw *hw,

				      unsigned long parent_rate)

{
@@ -143,10 +108,8 @@ unsigned long omap2_clk_apll96_recalc(struct clk_hw *hw, 
{

	return (omap2xxx_clk_apll_locked(hw)) ? 96000000 : 0;

}

#endif



/* Public data */

#ifdef CONFIG_COMMON_CLK

const struct clk_hw_omap_ops clkhwops_apll54 = {

	.allow_idle	= _apll54_allow_idle,

	.deny_idle	= _apll54_deny_idle,
@@ -156,21 +119,6 @@ const struct clk_hw_omap_ops clkhwops_apll96 = { 
	.allow_idle	= _apll96_allow_idle,

	.deny_idle	= _apll96_deny_idle,

};

#else

const struct clkops clkops_apll96 = {

	.enable		= _apll96_enable,

	.disable	= _apll96_disable,

	.allow_idle	= _apll96_allow_idle,

	.deny_idle	= _apll96_deny_idle,

};



const struct clkops clkops_apll54 = {

	.enable		= _apll54_enable,

	.disable	= _apll54_disable,

	.allow_idle	= _apll54_allow_idle,

	.deny_idle	= _apll54_deny_idle,

};

#endif



/* Public functions */

arch/arm/mach-omap2/clkt2xxx_dpll.c

+0 −16
Original line number Diff line number Diff line
@@ -29,11 +29,7 @@ 
 * REVISIT: DPLL can optionally enter low-power bypass by writing 0x1

 * instead.  Add some mechanism to optionally enter this mode.

 */

#ifdef CONFIG_COMMON_CLK

static void _allow_idle(struct clk_hw_omap *clk)

#else

static void _allow_idle(struct clk *clk)

#endif

{

	if (!clk || !clk->dpll_data)

		return;
@@ -47,11 +43,7 @@ static void _allow_idle(struct clk *clk) 
 *

 * Disable DPLL automatic idle control.  No return value.

 */

#ifdef CONFIG_COMMON_CLK

static void _deny_idle(struct clk_hw_omap *clk)

#else

static void _deny_idle(struct clk *clk)

#endif

{

	if (!clk || !clk->dpll_data)

		return;
@@ -61,15 +53,7 @@ static void _deny_idle(struct clk *clk) 




/* Public data */

#ifdef CONFIG_COMMON_CLK

const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll = {

	.allow_idle	= _allow_idle,

	.deny_idle	= _deny_idle,

};
 
#else

const struct clkops clkops_omap2xxx_dpll_ops = {

	.allow_idle	= _allow_idle,

	.deny_idle	= _deny_idle,

};

#endif

arch/arm/mach-omap2/clkt2xxx_dpllcore.c

+0 −21
Original line number Diff line number Diff line
@@ -41,11 +41,7 @@ 
 * (currently defined as "dpll_ck" in the OMAP2xxx clock tree).  Set

 * during dpll_ck init and used later by omap2xxx_clk_get_core_rate().

 */

#ifdef CONFIG_COMMON_CLK

static struct clk_hw_omap *dpll_core_ck;

#else

static struct clk *dpll_core_ck;

#endif



/**

 * omap2xxx_clk_get_core_rate - return the CORE_CLK rate
@@ -109,25 +105,16 @@ static long omap2_dpllcore_round_rate(unsigned long target_rate) 


}



#ifdef CONFIG_COMMON_CLK

unsigned long omap2_dpllcore_recalc(struct clk_hw *hw,

				    unsigned long parent_rate)

#else

unsigned long omap2_dpllcore_recalc(struct clk *clk)

#endif

{

	return omap2xxx_clk_get_core_rate();

}



#ifdef CONFIG_COMMON_CLK

int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate,

			     unsigned long parent_rate)

{

	struct clk_hw_omap *clk = to_clk_hw_omap(hw);

#else

int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)

{

#endif

	u32 cur_rate, low, mult, div, valid_rate, done_rate;

	u32 bypass = 0;

	struct prcm_config tmpset;
@@ -205,16 +192,8 @@ int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) 
 * statically defined, this code may need to change to increment some

 * kind of use count on dpll_ck.

 */

#ifdef CONFIG_COMMON_CLK

void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw)

#else

void omap2xxx_clkt_dpllcore_init(struct clk *clk)

#endif

{

	WARN(dpll_core_ck, "dpll_core_ck already set - should never happen");

#ifdef CONFIG_COMMON_CLK

	dpll_core_ck = to_clk_hw_omap(hw);

#else

	dpll_core_ck = clk;

#endif

}

arch/arm/mach-omap2/clkt2xxx_osc.c

+0 −20
Original line number Diff line number Diff line
@@ -35,11 +35,7 @@ 
 * clk_enable/clk_disable()-based usecounting for osc_ck should be

 * replaced with autoidle-based usecounting.

 */

#ifdef CONFIG_COMMON_CLK

int omap2_enable_osc_ck(struct clk_hw *clk)

#else

static int omap2_enable_osc_ck(struct clk *clk)

#endif

{

	u32 pcc;
@@ -57,11 +53,7 @@ static int omap2_enable_osc_ck(struct clk *clk) 
 * clk_enable/clk_disable()-based usecounting for osc_ck should be

 * replaced with autoidle-based usecounting.

 */

#ifdef CONFIG_COMMON_CLK

void omap2_disable_osc_ck(struct clk_hw *clk)

#else

static void omap2_disable_osc_ck(struct clk *clk)

#endif

{

	u32 pcc;
@@ -70,20 +62,8 @@ static void omap2_disable_osc_ck(struct clk *clk) 
	__raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);

}



#ifndef CONFIG_COMMON_CLK

const struct clkops clkops_oscck = {

	.enable		= omap2_enable_osc_ck,

	.disable	= omap2_disable_osc_ck,

};

#endif



#ifdef CONFIG_COMMON_CLK

unsigned long omap2_osc_clk_recalc(struct clk_hw *clk,

				   unsigned long parent_rate)

#else

unsigned long omap2_osc_clk_recalc(struct clk *clk)

#endif

{

	return omap2xxx_get_apll_clkin() * omap2xxx_get_sysclkdiv();

}

arch/arm/mach-omap2/clkt2xxx_sys.c

+0 −8
Original line number Diff line number Diff line
@@ -40,16 +40,8 @@ u32 omap2xxx_get_sysclkdiv(void) 
	return div;

}



#ifdef CONFIG_COMMON_CLK

unsigned long omap2xxx_sys_clk_recalc(struct clk_hw *clk,

				      unsigned long parent_rate)

{

	return parent_rate / omap2xxx_get_sysclkdiv();

}
 
#else

unsigned long omap2xxx_sys_clk_recalc(struct clk *clk)

{

	return clk->parent->rate / omap2xxx_get_sysclkdiv();

}

#endif