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Commit d0312d7e authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'imx-cleanup' of git://git.pengutronix.de/git/imx/linux-2.6 into next/cleanup 

ARM i.MX cleanup patches

* tag 'imx-cleanup' of git://git.pengutronix.de/git/imx/linux-2.6:
  ARM i.MX53 clk: Fix ldb parent clocks
  serial/imx: fix IMX UART macro usage to reflect correct processor
  ARM: i.MX remove last leftovers from legacy clock support
  ARM: i.MX clk pllv1: move mxc_decode_pll code to its user
  ARM: imx27-phytec-phycore: Fix I2C EEPROM address
  ARM i.MX mx2_camera: Remove MX2_CAMERA_SWAP16 and MX2_CAMERA_PACK_DIR_MSB flags.
  ARM i.MX: remove duplicated include from clk-imx21.c
  ARM: plat-mxc: Remove unused imx_ioremap
parents 025c95a6 51f66191

arch/arm/boot/dts/imx27-phytec-phycore.dts

+1 −1
Original line number Original line Diff line number Diff line
@@ -49,7 +49,7 @@ 
			i2c@1001d000 {

			i2c@1001d000 {

				clock-frequency = <400000>;

				clock-frequency = <400000>;

				status = "okay";

				status = "okay";

				at24@4c {

				at24@52 {

					compatible = "at,24c32";

					compatible = "at,24c32";

					pagesize = <32>;

					pagesize = <32>;

					reg = <0x52>;

					reg = <0x52>;

arch/arm/mach-imx/Makefile

+1 −1
Original line number Original line Diff line number Diff line
@@ -13,7 +13,7 @@ imx5-pm-$(CONFIG_PM) += pm-imx5.o 
obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(imx5-pm-y) cpu_op-mx51.o

obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(imx5-pm-y) cpu_op-mx51.o





obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \

obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \

			    clk-pfd.o clk-busy.o

			    clk-pfd.o clk-busy.o clk.o





# Support for CMOS sensor interface

# Support for CMOS sensor interface

obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o

obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o

arch/arm/mach-imx/clk-imx21.c

+0 −1
Original line number Original line Diff line number Diff line
@@ -23,7 +23,6 @@ 
#include <linux/clk-provider.h>

#include <linux/clk-provider.h>

#include <linux/io.h>

#include <linux/io.h>

#include <linux/module.h>

#include <linux/module.h>

#include <linux/clkdev.h>

#include <linux/err.h>

#include <linux/err.h>





#include <mach/hardware.h>

#include <mach/hardware.h>

arch/arm/mach-imx/clk-imx51-imx53.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -39,10 +39,10 @@ static const char *ssi_ext2_com_sels[] = { "ssi_ext2_podf", "ssi2_root_gate", }; 
static const char *emi_slow_sel[] = { "main_bus", "ahb", };

static const char *emi_slow_sel[] = { "main_bus", "ahb", };

static const char *usb_phy_sel_str[] = { "osc", "usb_phy_podf", };

static const char *usb_phy_sel_str[] = { "osc", "usb_phy_podf", };

static const char *mx51_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "tve_di", };

static const char *mx51_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "tve_di", };

static const char *mx53_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "di_pll4_podf", "dummy", "ldb_di0", };

static const char *mx53_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "di_pll4_podf", "dummy", "ldb_di0_gate", };

static const char *mx53_ldb_di0_sel[] = { "pll3_sw", "pll4_sw", };

static const char *mx53_ldb_di0_sel[] = { "pll3_sw", "pll4_sw", };

static const char *mx51_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", };

static const char *mx51_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", };

static const char *mx53_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", "ldb_di1", };

static const char *mx53_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", "ldb_di1_gate", };

static const char *mx53_ldb_di1_sel[] = { "pll3_sw", "pll4_sw", };

static const char *mx53_ldb_di1_sel[] = { "pll3_sw", "pll4_sw", };

static const char *mx51_tve_ext_sel[] = { "osc", "ckih1", };

static const char *mx51_tve_ext_sel[] = { "osc", "ckih1", };

static const char *mx53_tve_ext_sel[] = { "pll4_sw", "ckih1", };

static const char *mx53_tve_ext_sel[] = { "pll4_sw", "ckih1", };

arch/arm/mach-imx/clk-pllv1.c

+47 −2
Original line number Original line Diff line number Diff line
@@ -6,7 +6,7 @@ 
#include <linux/err.h>

#include <linux/err.h>

#include <mach/common.h>

#include <mach/common.h>

#include <mach/hardware.h>

#include <mach/hardware.h>

#include <mach/clock.h>



#include "clk.h"

#include "clk.h"





/**

/**
@@ -29,8 +29,53 @@ static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw, 
		unsigned long parent_rate)

		unsigned long parent_rate)

{

{

	struct clk_pllv1 *pll = to_clk_pllv1(hw);

	struct clk_pllv1 *pll = to_clk_pllv1(hw);

	long long ll;

	int mfn_abs;

	unsigned int mfi, mfn, mfd, pd;

	u32 reg;

	unsigned long rate;



	reg = readl(pll->base);



	/*

	 * Get the resulting clock rate from a PLL register value and the input

	 * frequency. PLLs with this register layout can be found on i.MX1,

	 * i.MX21, i.MX27 and i,MX31

	 *

	 *                  mfi + mfn / (mfd + 1)

	 *  f = 2 * f_ref * --------------------

	 *                        pd + 1

	 */



	mfi = (reg >> 10) & 0xf;

	mfn = reg & 0x3ff;

	mfd = (reg >> 16) & 0x3ff;

	pd =  (reg >> 26) & 0xf;



	mfi = mfi <= 5 ? 5 : mfi;



	mfn_abs = mfn;



	/*

	 * On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit

	 * 2's complements number

	 */

	if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)

		mfn_abs = 0x400 - mfn;



	rate = parent_rate * 2;

	rate /= pd + 1;



	ll = (unsigned long long)rate * mfn_abs;



	do_div(ll, mfd + 1);



	if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)

		ll = -ll;



	ll = (rate * mfi) + ll;





	return mxc_decode_pll(readl(pll->base), parent_rate);

	return ll;

}

}





struct clk_ops clk_pllv1_ops = {

struct clk_ops clk_pllv1_ops = {