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Commit d0172347 authored by Marc Zyngier's avatar Marc Zyngier Committed by Will Deacon
Browse files

ARM: virt: simplify __hyp_stub_install epilog 



__hyp_stub_install duplicates quite a bit of safe_svcmode_maskall
by forcing the CPU back to SVC. This is unnecessary, as
safe_svcmode_maskall is called just after.

Furthermore, the way we build SPSR_hyp is buggy as we fail to mask
the interrupts, leading to interesting behaviours on TC2 + UEFI.

The fix is to simply remove this code and rely on safe_svcmode_maskall
to do the right thing.

Cc: <stable@vger.kernel.org>
Reviewed-by: default avatarDave Martin <dave.martin@linaro.org>
Reported-by: default avatarHarry Liebel <harry.liebel@arm.com>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent 6e484be1

arch/arm/kernel/hyp-stub.S

+3 −9
Original line number Diff line number Diff line
@@ -120,7 +120,8 @@ ENTRY(__hyp_stub_install_secondary) 
 * Eventually, CPU-specific code might be needed -- assume not for now

 *

 * This code relies on the "eret" instruction to synchronize the

 * various coprocessor accesses.

 * various coprocessor accesses. This is done when we switch to SVC

 * (see safe_svcmode_maskall).

 */

	@ Now install the hypervisor stub:

	adr	r7, __hyp_stub_vectors
@@ -155,14 +156,7 @@ THUMB( orr r7, #(1 << 30) ) @ HSCTLR.TE 
1:

#endif



	bic	r7, r4, #MODE_MASK

	orr	r7, r7, #SVC_MODE

THUMB(	orr	r7, r7, #PSR_T_BIT	)

	msr	spsr_cxsf, r7		@ This is SPSR_hyp.



	__MSR_ELR_HYP(14)		@ msr elr_hyp, lr

	__ERET				@ return, switching to SVC mode

					@ The boot CPU mode is left in r4.

	bx	lr			@ The boot CPU mode is left in r4.

ENDPROC(__hyp_stub_install_secondary)



__hyp_stub_do_trap: