drm/amdgpu: rename amdgpu_dpm_funcs to amd_pm_funcs

}

struct amd_vce_state*

amdgpu_get_vce_clock_state(struct amdgpu_device *adev, unsigned idx)

amdgpu_get_vce_clock_state(void *handle, u32 idx)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	if (idx < adev->pm.dpm.num_of_vce_states)

		return &adev->pm.dpm.vce_states[idx];

	AMDGPU_PCIE_GEN_INVALID = 0xffff

};

struct amdgpu_dpm_funcs {

	int (*get_temperature)(struct amdgpu_device *adev);

	int (*pre_set_power_state)(struct amdgpu_device *adev);

	int (*set_power_state)(struct amdgpu_device *adev);

	void (*post_set_power_state)(struct amdgpu_device *adev);

	void (*display_configuration_changed)(struct amdgpu_device *adev);

	u32 (*get_sclk)(struct amdgpu_device *adev, bool low);

	u32 (*get_mclk)(struct amdgpu_device *adev, bool low);

	void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps);

	void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m);

	int (*force_performance_level)(struct amdgpu_device *adev, enum amd_dpm_forced_level level);

	bool (*vblank_too_short)(struct amdgpu_device *adev);

	void (*powergate_uvd)(struct amdgpu_device *adev, bool gate);

	void (*powergate_vce)(struct amdgpu_device *adev, bool gate);

	void (*enable_bapm)(struct amdgpu_device *adev, bool enable);

	void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode);

	u32 (*get_fan_control_mode)(struct amdgpu_device *adev);

	int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed);

	int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed);

	int (*force_clock_level)(struct amdgpu_device *adev, enum pp_clock_type type, uint32_t mask);

	int (*print_clock_levels)(struct amdgpu_device *adev, enum pp_clock_type type, char *buf);

	int (*get_sclk_od)(struct amdgpu_device *adev);

	int (*set_sclk_od)(struct amdgpu_device *adev, uint32_t value);

	int (*get_mclk_od)(struct amdgpu_device *adev);

	int (*set_mclk_od)(struct amdgpu_device *adev, uint32_t value);

	int (*check_state_equal)(struct amdgpu_device *adev,

				struct amdgpu_ps *cps,

				struct amdgpu_ps *rps,

				bool *equal);

	int (*read_sensor)(struct amdgpu_device *adev, int idx, void *value,

			   int *size);

	struct amd_vce_state* (*get_vce_clock_state)(struct amdgpu_device *adev, unsigned idx);

	int (*reset_power_profile_state)(struct amdgpu_device *adev,

			struct amd_pp_profile *request);

	int (*get_power_profile_state)(struct amdgpu_device *adev,

			struct amd_pp_profile *query);

	int (*set_power_profile_state)(struct amdgpu_device *adev,

			struct amd_pp_profile *request);

	int (*switch_power_profile)(struct amdgpu_device *adev,

			enum amd_pp_profile_type type);

};

#define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))

#define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))

#define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))

	struct amdgpu_dpm       dpm;

	const struct firmware	*fw;	/* SMC firmware */

	uint32_t                fw_version;

	const struct amdgpu_dpm_funcs *funcs;

	const struct amd_pm_funcs *funcs;

	uint32_t                pcie_gen_mask;

	uint32_t                pcie_mlw_mask;

	struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */

u8 amdgpu_encode_pci_lane_width(u32 lanes);

struct amd_vce_state*

amdgpu_get_vce_clock_state(struct amdgpu_device *adev, unsigned idx);

amdgpu_get_vce_clock_state(void *handle, u32 idx);

#endif

	return ret;

}

static void ci_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate)

static void ci_dpm_powergate_uvd(void *handle, bool gate)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	struct ci_power_info *pi = ci_get_pi(adev);

	pi->uvd_power_gated = gate;

	}

}

static bool ci_dpm_vblank_too_short(struct amdgpu_device *adev)

static bool ci_dpm_vblank_too_short(void *handle)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);

	u32 switch_limit = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 300;

	}

}

static int ci_dpm_get_fan_speed_percent(struct amdgpu_device *adev,

static int ci_dpm_get_fan_speed_percent(void *handle,

					u32 *speed)

{

	u32 duty, duty100;

	u64 tmp64;

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	if (adev->pm.no_fan)

		return -ENOENT;

	return 0;

}

static int ci_dpm_set_fan_speed_percent(struct amdgpu_device *adev,

static int ci_dpm_set_fan_speed_percent(void *handle,

					u32 speed)

{

	u32 tmp;

	u32 duty, duty100;

	u64 tmp64;

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	struct ci_power_info *pi = ci_get_pi(adev);

	if (adev->pm.no_fan)

	return 0;

}

static void ci_dpm_set_fan_control_mode(struct amdgpu_device *adev, u32 mode)

static void ci_dpm_set_fan_control_mode(void *handle, u32 mode)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	switch (mode) {

	case AMD_FAN_CTRL_NONE:

		if (adev->pm.dpm.fan.ucode_fan_control)

	}

}

static u32 ci_dpm_get_fan_control_mode(struct amdgpu_device *adev)

static u32 ci_dpm_get_fan_control_mode(void *handle)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	struct ci_power_info *pi = ci_get_pi(adev);

	if (pi->fan_is_controlled_by_smc)

}

static int ci_dpm_force_performance_level(struct amdgpu_device *adev,

static int ci_dpm_force_performance_level(void *handle,

					  enum amd_dpm_forced_level level)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	struct ci_power_info *pi = ci_get_pi(adev);

	u32 tmp, levels, i;

	int ret;

	adev->pm.dpm.requested_ps = &pi->requested_rps;

}

static int ci_dpm_pre_set_power_state(struct amdgpu_device *adev)

static int ci_dpm_pre_set_power_state(void *handle)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	struct ci_power_info *pi = ci_get_pi(adev);

	struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;

	struct amdgpu_ps *new_ps = &requested_ps;

	return 0;

}

static void ci_dpm_post_set_power_state(struct amdgpu_device *adev)

static void ci_dpm_post_set_power_state(void *handle)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	struct ci_power_info *pi = ci_get_pi(adev);

	struct amdgpu_ps *new_ps = &pi->requested_rps;

	ci_update_current_ps(adev, boot_ps);

}

static int ci_dpm_set_power_state(struct amdgpu_device *adev)

static int ci_dpm_set_power_state(void *handle)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	struct ci_power_info *pi = ci_get_pi(adev);

	struct amdgpu_ps *new_ps = &pi->requested_rps;

	struct amdgpu_ps *old_ps = &pi->current_rps;

}

#endif

static void ci_dpm_display_configuration_changed(struct amdgpu_device *adev)

static void ci_dpm_display_configuration_changed(void *handle)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	ci_program_display_gap(adev);

}

}

static void

ci_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,

ci_dpm_debugfs_print_current_performance_level(void *handle,

					       struct seq_file *m)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	struct ci_power_info *pi = ci_get_pi(adev);

	struct amdgpu_ps *rps = &pi->current_rps;

	u32 sclk = ci_get_average_sclk_freq(adev);

	seq_printf(m, "GPU load: %u %%\n", activity_percent);

}

static void ci_dpm_print_power_state(struct amdgpu_device *adev,

				     struct amdgpu_ps *rps)

static void ci_dpm_print_power_state(void *handle, void *current_ps)

{

	struct amdgpu_ps *rps = (struct amdgpu_ps *)current_ps;

	struct ci_ps *ps = ci_get_ps(rps);

	struct ci_pl *pl;

	int i;

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	amdgpu_dpm_print_class_info(rps->class, rps->class2);

	amdgpu_dpm_print_cap_info(rps->caps);

		  (ci_cpl1->pcie_lane == ci_cpl2->pcie_lane));

}

static int ci_check_state_equal(struct amdgpu_device *adev,

				struct amdgpu_ps *cps,

				struct amdgpu_ps *rps,

static int ci_check_state_equal(void *handle,

				void *current_ps,

				void *request_ps,

				bool *equal)

{

	struct ci_ps *ci_cps;

	struct ci_ps *ci_rps;

	int i;

	struct amdgpu_ps *cps = (struct amdgpu_ps *)current_ps;

	struct amdgpu_ps *rps = (struct amdgpu_ps *)request_ps;

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	if (adev == NULL || cps == NULL || rps == NULL || equal == NULL)

		return -EINVAL;

	ci_cps = ci_get_ps(cps);

	ci_rps = ci_get_ps(rps);

	ci_cps = ci_get_ps((struct amdgpu_ps *)cps);

	ci_rps = ci_get_ps((struct amdgpu_ps *)rps);

	if (ci_cps == NULL) {

		*equal = false;

	return 0;

}

static u32 ci_dpm_get_sclk(struct amdgpu_device *adev, bool low)

static u32 ci_dpm_get_sclk(void *handle, bool low)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	struct ci_power_info *pi = ci_get_pi(adev);

	struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);

		return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;

}

static u32 ci_dpm_get_mclk(struct amdgpu_device *adev, bool low)

static u32 ci_dpm_get_mclk(void *handle, bool low)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	struct ci_power_info *pi = ci_get_pi(adev);

	struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);

}

/* get temperature in millidegrees */

static int ci_dpm_get_temp(struct amdgpu_device *adev)

static int ci_dpm_get_temp(void *handle)

{

	u32 temp;

	int actual_temp = 0;

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	temp = (RREG32_SMC(ixCG_MULT_THERMAL_STATUS) & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>

		CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;

	return 0;

}

static int ci_dpm_print_clock_levels(struct amdgpu_device *adev,

static int ci_dpm_print_clock_levels(void *handle,

		enum pp_clock_type type, char *buf)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	struct ci_power_info *pi = ci_get_pi(adev);

	struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table;

	struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table;

	return size;

}

static int ci_dpm_force_clock_level(struct amdgpu_device *adev,

static int ci_dpm_force_clock_level(void *handle,

		enum pp_clock_type type, uint32_t mask)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	struct ci_power_info *pi = ci_get_pi(adev);

	if (adev->pm.dpm.forced_level & (AMD_DPM_FORCED_LEVEL_AUTO |

	return 0;

}

static int ci_dpm_get_sclk_od(struct amdgpu_device *adev)

static int ci_dpm_get_sclk_od(void *handle)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	struct ci_power_info *pi = ci_get_pi(adev);

	struct ci_single_dpm_table *sclk_table = &(pi->dpm_table.sclk_table);

	struct ci_single_dpm_table *golden_sclk_table =

	return value;

}

static int ci_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value)

static int ci_dpm_set_sclk_od(void *handle, uint32_t value)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	struct ci_power_info *pi = ci_get_pi(adev);

	struct ci_ps *ps = ci_get_ps(adev->pm.dpm.requested_ps);

	struct ci_single_dpm_table *golden_sclk_table =

	return 0;

}

static int ci_dpm_get_mclk_od(struct amdgpu_device *adev)

static int ci_dpm_get_mclk_od(void *handle)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	struct ci_power_info *pi = ci_get_pi(adev);

	struct ci_single_dpm_table *mclk_table = &(pi->dpm_table.mclk_table);

	struct ci_single_dpm_table *golden_mclk_table =

	return value;

}

static int ci_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value)

static int ci_dpm_set_mclk_od(void *handle, uint32_t value)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	struct ci_power_info *pi = ci_get_pi(adev);

	struct ci_ps *ps = ci_get_ps(adev->pm.dpm.requested_ps);

	struct ci_single_dpm_table *golden_mclk_table =

	return 0;

}

static int ci_dpm_get_power_profile_state(struct amdgpu_device *adev,

static int ci_dpm_get_power_profile_state(void *handle,

		struct amd_pp_profile *query)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	struct ci_power_info *pi = ci_get_pi(adev);

	if (!pi || !query)

	return result;

}

static int ci_dpm_set_power_profile_state(struct amdgpu_device *adev,

static int ci_dpm_set_power_profile_state(void *handle,

		struct amd_pp_profile *request)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	struct ci_power_info *pi = ci_get_pi(adev);

	int ret = -1;

	return 0;

}

static int ci_dpm_reset_power_profile_state(struct amdgpu_device *adev,

static int ci_dpm_reset_power_profile_state(void *handle,

		struct amd_pp_profile *request)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	struct ci_power_info *pi = ci_get_pi(adev);

	if (!pi || !request)

		return -EINVAL;

}

static int ci_dpm_switch_power_profile(struct amdgpu_device *adev,

static int ci_dpm_switch_power_profile(void *handle,

		enum amd_pp_profile_type type)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	struct ci_power_info *pi = ci_get_pi(adev);

	struct amd_pp_profile request = {0};

	return 0;

}

static int ci_dpm_read_sensor(struct amdgpu_device *adev, int idx,

static int ci_dpm_read_sensor(void *handle, int idx,

			      void *value, int *size)

{

	u32 activity_percent = 50;

	int ret;

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	/* size must be at least 4 bytes for all sensors */

	if (*size < 4)

	.set_powergating_state = ci_dpm_set_powergating_state,

};

static const struct amdgpu_dpm_funcs ci_dpm_funcs = {

static const struct amd_pm_funcs ci_dpm_funcs = {

	.get_temperature = &ci_dpm_get_temp,

	.pre_set_power_state = &ci_dpm_pre_set_power_state,

	.set_power_state = &ci_dpm_set_power_state,

					    int min_temp, int max_temp);

static int kv_init_fps_limits(struct amdgpu_device *adev);

static void kv_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate);

static void kv_dpm_powergate_uvd(void *handle, bool gate);

static void kv_dpm_powergate_vce(struct amdgpu_device *adev, bool gate);

static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate);

static void kv_dpm_powergate_acp(struct amdgpu_device *adev, bool gate);

	adev->pm.dpm.requested_ps = &pi->requested_rps;

}

static void kv_dpm_enable_bapm(struct amdgpu_device *adev, bool enable)

static void kv_dpm_enable_bapm(void *handle, bool enable)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	struct kv_power_info *pi = kv_get_pi(adev);

	int ret;

	return kv_enable_acp_dpm(adev, !gate);

}

static void kv_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate)

static void kv_dpm_powergate_uvd(void *handle, bool gate)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	struct kv_power_info *pi = kv_get_pi(adev);

	int ret;

	return ret;

}

static int kv_dpm_force_performance_level(struct amdgpu_device *adev,

static int kv_dpm_force_performance_level(void *handle,

					  enum amd_dpm_forced_level level)

{

	int ret;

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	if (level == AMD_DPM_FORCED_LEVEL_HIGH) {

		ret = kv_force_dpm_highest(adev);

	return 0;

}

static int kv_dpm_pre_set_power_state(struct amdgpu_device *adev)

static int kv_dpm_pre_set_power_state(void *handle)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	struct kv_power_info *pi = kv_get_pi(adev);

	struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;

	struct amdgpu_ps *new_ps = &requested_ps;

	return 0;

}

static int kv_dpm_set_power_state(struct amdgpu_device *adev)

static int kv_dpm_set_power_state(void *handle)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	struct kv_power_info *pi = kv_get_pi(adev);

	struct amdgpu_ps *new_ps = &pi->requested_rps;

	struct amdgpu_ps *old_ps = &pi->current_rps;

	return 0;

}

static void kv_dpm_post_set_power_state(struct amdgpu_device *adev)

static void kv_dpm_post_set_power_state(void *handle)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	struct kv_power_info *pi = kv_get_pi(adev);

	struct amdgpu_ps *new_ps = &pi->requested_rps;

}

static void

kv_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,

kv_dpm_debugfs_print_current_performance_level(void *handle,

					       struct seq_file *m)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	struct kv_power_info *pi = kv_get_pi(adev);

	u32 current_index =

		(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &

}

static void

kv_dpm_print_power_state(struct amdgpu_device *adev,