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Commit cf532232 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2016-11-09' of git://anongit.freedesktop.org/drm-intel into drm-fixes 

i915 fixes, include Sandybridge rendering regression fix.

* tag 'drm-intel-fixes-2016-11-09' of git://anongit.freedesktop.org/drm-intel:
  drm/i915: Limit Valleyview and earlier to only using mappable scanout
  drm/i915: Round tile chunks up for constructing partial VMAs
  drm/i915/dp: Extend BDW DP audio workaround to GEN9 platforms
  drm/i915/dp: BDW cdclk fix for DP audio
  drm/i915/vlv: Prevent enabling hpd polling in late suspend
  drm/i915: Respect alternate_ddc_pin for all DDI ports
parents 020a0bbc 54905ab5

drivers/gpu/drm/i915/i915_gem.c

+17 −3
Original line number Diff line number Diff line
@@ -1806,7 +1806,7 @@ int i915_gem_fault(struct vm_area_struct *area, struct vm_fault *vmf) 
		/* Use a partial view if it is bigger than available space */

		chunk_size = MIN_CHUNK_PAGES;

		if (i915_gem_object_is_tiled(obj))

			chunk_size = max(chunk_size, tile_row_pages(obj));

			chunk_size = roundup(chunk_size, tile_row_pages(obj));



		memset(&view, 0, sizeof(view));

		view.type = I915_GGTT_VIEW_PARTIAL;
@@ -3543,8 +3543,22 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, 
	if (view->type == I915_GGTT_VIEW_NORMAL)

		vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment,

					       PIN_MAPPABLE | PIN_NONBLOCK);

	if (IS_ERR(vma))

		vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, 0);

	if (IS_ERR(vma)) {

		struct drm_i915_private *i915 = to_i915(obj->base.dev);

		unsigned int flags;



		/* Valleyview is definitely limited to scanning out the first

		 * 512MiB. Lets presume this behaviour was inherited from the

		 * g4x display engine and that all earlier gen are similarly

		 * limited. Testing suggests that it is a little more

		 * complicated than this. For example, Cherryview appears quite

		 * happy to scanout from anywhere within its global aperture.

		 */

		flags = 0;

		if (HAS_GMCH_DISPLAY(i915))

			flags = PIN_MAPPABLE;

		vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, flags);

	}

	if (IS_ERR(vma))

		goto err_unpin_display;

drivers/gpu/drm/i915/intel_display.c

+26 −3
Original line number Diff line number Diff line
@@ -10243,6 +10243,29 @@ static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state) 
	bxt_set_cdclk(to_i915(dev), req_cdclk);

}



static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,

					  int pixel_rate)

{

	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);



	/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */

	if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)

		pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);



	/* BSpec says "Do not use DisplayPort with CDCLK less than

	 * 432 MHz, audio enabled, port width x4, and link rate

	 * HBR2 (5.4 GHz), or else there may be audio corruption or

	 * screen corruption."

	 */

	if (intel_crtc_has_dp_encoder(crtc_state) &&

	    crtc_state->has_audio &&

	    crtc_state->port_clock >= 540000 &&

	    crtc_state->lane_count == 4)

		pixel_rate = max(432000, pixel_rate);



	return pixel_rate;

}



/* compute the max rate for new configuration */

static int ilk_max_pixel_rate(struct drm_atomic_state *state)

{
@@ -10268,9 +10291,9 @@ static int ilk_max_pixel_rate(struct drm_atomic_state *state) 


		pixel_rate = ilk_pipe_pixel_rate(crtc_state);



		/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */

		if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)

			pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);

		if (IS_BROADWELL(dev_priv) || IS_GEN9(dev_priv))

			pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state,

								    pixel_rate);



		intel_state->min_pixclk[i] = pixel_rate;

	}

drivers/gpu/drm/i915/intel_hdmi.c

+48 −36
Original line number Diff line number Diff line
@@ -1799,6 +1799,50 @@ intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *c 
	intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;

}



static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,

			     enum port port)

{

	const struct ddi_vbt_port_info *info =

		&dev_priv->vbt.ddi_port_info[port];

	u8 ddc_pin;



	if (info->alternate_ddc_pin) {

		DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n",

			      info->alternate_ddc_pin, port_name(port));

		return info->alternate_ddc_pin;

	}



	switch (port) {

	case PORT_B:

		if (IS_BROXTON(dev_priv))

			ddc_pin = GMBUS_PIN_1_BXT;

		else

			ddc_pin = GMBUS_PIN_DPB;

		break;

	case PORT_C:

		if (IS_BROXTON(dev_priv))

			ddc_pin = GMBUS_PIN_2_BXT;

		else

			ddc_pin = GMBUS_PIN_DPC;

		break;

	case PORT_D:

		if (IS_CHERRYVIEW(dev_priv))

			ddc_pin = GMBUS_PIN_DPD_CHV;

		else

			ddc_pin = GMBUS_PIN_DPD;

		break;

	default:

		MISSING_CASE(port);

		ddc_pin = GMBUS_PIN_DPB;

		break;

	}



	DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n",

		      ddc_pin, port_name(port));



	return ddc_pin;

}



void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,

			       struct intel_connector *intel_connector)

{
@@ -1808,7 +1852,6 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, 
	struct drm_device *dev = intel_encoder->base.dev;

	struct drm_i915_private *dev_priv = to_i915(dev);

	enum port port = intel_dig_port->port;

	uint8_t alternate_ddc_pin;



	DRM_DEBUG_KMS("Adding HDMI connector on port %c\n",

		      port_name(port));
@@ -1826,12 +1869,10 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, 
	connector->doublescan_allowed = 0;

	connector->stereo_allowed = 1;



	intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);



	switch (port) {

	case PORT_B:

		if (IS_BROXTON(dev_priv))

			intel_hdmi->ddc_bus = GMBUS_PIN_1_BXT;

		else

			intel_hdmi->ddc_bus = GMBUS_PIN_DPB;

		/*

		 * On BXT A0/A1, sw needs to activate DDIA HPD logic and

		 * interrupts to check the external panel connection.
@@ -1842,46 +1883,17 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, 
			intel_encoder->hpd_pin = HPD_PORT_B;

		break;

	case PORT_C:

		if (IS_BROXTON(dev_priv))

			intel_hdmi->ddc_bus = GMBUS_PIN_2_BXT;

		else

			intel_hdmi->ddc_bus = GMBUS_PIN_DPC;

		intel_encoder->hpd_pin = HPD_PORT_C;

		break;

	case PORT_D:

		if (WARN_ON(IS_BROXTON(dev_priv)))

			intel_hdmi->ddc_bus = GMBUS_PIN_DISABLED;

		else if (IS_CHERRYVIEW(dev_priv))

			intel_hdmi->ddc_bus = GMBUS_PIN_DPD_CHV;

		else

			intel_hdmi->ddc_bus = GMBUS_PIN_DPD;

		intel_encoder->hpd_pin = HPD_PORT_D;

		break;

	case PORT_E:

		/* On SKL PORT E doesn't have seperate GMBUS pin

		 *  We rely on VBT to set a proper alternate GMBUS pin. */

		alternate_ddc_pin =

			dev_priv->vbt.ddi_port_info[PORT_E].alternate_ddc_pin;

		switch (alternate_ddc_pin) {

		case DDC_PIN_B:

			intel_hdmi->ddc_bus = GMBUS_PIN_DPB;

			break;

		case DDC_PIN_C:

			intel_hdmi->ddc_bus = GMBUS_PIN_DPC;

			break;

		case DDC_PIN_D:

			intel_hdmi->ddc_bus = GMBUS_PIN_DPD;

			break;

		default:

			MISSING_CASE(alternate_ddc_pin);

		}

		intel_encoder->hpd_pin = HPD_PORT_E;

		break;

	case PORT_A:

		intel_encoder->hpd_pin = HPD_PORT_A;

		/* Internal port only for eDP. */

	default:

		BUG();

		MISSING_CASE(port);

		return;

	}



	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {

drivers/gpu/drm/i915/intel_runtime_pm.c

+3 −1
Original line number Diff line number Diff line
@@ -1139,6 +1139,8 @@ static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv) 


	intel_power_sequencer_reset(dev_priv);



	/* Prevent us from re-enabling polling on accident in late suspend */

	if (!dev_priv->drm.dev->power.is_suspended)

		intel_hpd_poll_init(dev_priv);

}