Loading drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver3.c +0 −14 Original line number Diff line number Diff line Loading @@ -293,20 +293,6 @@ static int cam_vfe_camif_ver3_resource_init( "failed to enable dsp clk, rc = %d", rc); } /* All auto clock gating disabled by default */ CAM_INFO(CAM_ISP, "overriding clock gating"); cam_io_w_mb(0xFFFFFFFF, camif_data->mem_base + camif_data->common_reg->core_cgc_ovd_0); cam_io_w_mb(0xFF, camif_data->mem_base + camif_data->common_reg->core_cgc_ovd_1); cam_io_w_mb(0x1, camif_data->mem_base + camif_data->common_reg->ahb_cgc_ovd); cam_io_w_mb(0x1, camif_data->mem_base + camif_data->common_reg->noc_cgc_ovd); return rc; } Loading drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver3.c +15 −0 Original line number Diff line number Diff line Loading @@ -222,9 +222,24 @@ int cam_vfe_top_ver3_init_hw(void *device_priv, void *init_hw_args, uint32_t arg_size) { struct cam_vfe_top_ver3_priv *top_priv = device_priv; struct cam_vfe_top_ver3_common_data common_data = top_priv->common_data; top_priv->hw_clk_rate = 0; /* Disable clock gating at IFE top */ CAM_INFO(CAM_ISP, "Disable clock gating at IFE top"); cam_soc_util_w_mb(common_data.soc_info, VFE_CORE_BASE_IDX, common_data.common_reg->core_cgc_ovd_0, 0xFFFFFFFF); cam_soc_util_w_mb(common_data.soc_info, VFE_CORE_BASE_IDX, common_data.common_reg->core_cgc_ovd_1, 0xFF); cam_soc_util_w_mb(common_data.soc_info, VFE_CORE_BASE_IDX, common_data.common_reg->ahb_cgc_ovd, 0x1); cam_soc_util_w_mb(common_data.soc_info, VFE_CORE_BASE_IDX, common_data.common_reg->noc_cgc_ovd, 0x1); return 0; } Loading Loading
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver3.c +0 −14 Original line number Diff line number Diff line Loading @@ -293,20 +293,6 @@ static int cam_vfe_camif_ver3_resource_init( "failed to enable dsp clk, rc = %d", rc); } /* All auto clock gating disabled by default */ CAM_INFO(CAM_ISP, "overriding clock gating"); cam_io_w_mb(0xFFFFFFFF, camif_data->mem_base + camif_data->common_reg->core_cgc_ovd_0); cam_io_w_mb(0xFF, camif_data->mem_base + camif_data->common_reg->core_cgc_ovd_1); cam_io_w_mb(0x1, camif_data->mem_base + camif_data->common_reg->ahb_cgc_ovd); cam_io_w_mb(0x1, camif_data->mem_base + camif_data->common_reg->noc_cgc_ovd); return rc; } Loading
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver3.c +15 −0 Original line number Diff line number Diff line Loading @@ -222,9 +222,24 @@ int cam_vfe_top_ver3_init_hw(void *device_priv, void *init_hw_args, uint32_t arg_size) { struct cam_vfe_top_ver3_priv *top_priv = device_priv; struct cam_vfe_top_ver3_common_data common_data = top_priv->common_data; top_priv->hw_clk_rate = 0; /* Disable clock gating at IFE top */ CAM_INFO(CAM_ISP, "Disable clock gating at IFE top"); cam_soc_util_w_mb(common_data.soc_info, VFE_CORE_BASE_IDX, common_data.common_reg->core_cgc_ovd_0, 0xFFFFFFFF); cam_soc_util_w_mb(common_data.soc_info, VFE_CORE_BASE_IDX, common_data.common_reg->core_cgc_ovd_1, 0xFF); cam_soc_util_w_mb(common_data.soc_info, VFE_CORE_BASE_IDX, common_data.common_reg->ahb_cgc_ovd, 0x1); cam_soc_util_w_mb(common_data.soc_info, VFE_CORE_BASE_IDX, common_data.common_reg->noc_cgc_ovd, 0x1); return 0; } Loading