Loading arch/arm64/boot/dts/qcom/kona-sde.dtsi +77 −2 Original line number Diff line number Diff line Loading @@ -7,10 +7,12 @@ compatible = "qcom,sde-kms"; reg = <0x0ae00000 0x84208>, <0x0aeb0000 0x2008>, <0x0aeac000 0x214>; <0x0aeac000 0x214>, <0x0ae8f000 0x02c>; reg-names = "mdp_phys", "vbif_phys", "regdma_phys"; "regdma_phys", "sid_phys"; clocks = <&clock_gcc GCC_DISP_AHB_CLK>, Loading @@ -32,9 +34,15 @@ /* interrupt config */ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <1>; iommus = <&apps_smmu 0x820 0x402>; qcom,iommu-dma = "disabled"; #address-cells = <1>; #size-cells = <0>; #power-domain-cells = <0>; /* hw blocks */ qcom,sde-off = <0x1000>; qcom,sde-len = <0x494>; Loading Loading @@ -301,4 +309,71 @@ <20000 20512 0 6400000>; }; }; mdss_rotator: qcom,mdss_rotator@aea8800 { compatible = "qcom,sde_rotator"; reg = <0x0ae00000 0xac000>, <0x0aeb8000 0x3000>; reg-names = "mdp_phys", "rot_vbif_phys"; #list-cells = <1>; qcom,mdss-rot-mode = <1>; qcom,mdss-highest-bank-bit = <0x3>; /* Bus Scale Settings */ qcom,msm-bus,name = "mdss_rotator"; qcom,msm-bus,num-cases = <3>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <25 512 0 0>, <25 512 0 6400000>, <25 512 0 6400000>; rot-vdd-supply = <&mdss_core_gdsc>; qcom,supply-names = "rot-vdd"; clocks = <&clock_gcc GCC_DISP_AHB_CLK>, <&clock_gcc GCC_DISP_SF_AXI_CLK>, <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, <&clock_dispcc DISP_CC_MDSS_ROT_CLK>; clock-names = "gcc_iface", "gcc_bus", "iface_clk", "rot_clk"; interrupt-parent = <&mdss_mdp>; interrupts = <2 0>; power-domains = <&mdss_mdp>; /* Offline rotator QoS setting */ qcom,mdss-rot-vbif-qos-setting = <3 3 3 3 3 3 3 3>; qcom,mdss-rot-vbif-memtype = <3 3>; qcom,mdss-rot-cdp-setting = <1 1>; qcom,mdss-rot-qos-lut = <0x0 0x0 0x0 0x0>; qcom,mdss-rot-danger-lut = <0x0 0x0>; qcom,mdss-rot-safe-lut = <0x0000ffff 0x0000ffff>; qcom,mdss-default-ot-rd-limit = <32>; qcom,mdss-default-ot-wr-limit = <32>; qcom,mdss-sbuf-headroom = <20>; /* reg bus scale settings */ rot_reg: qcom,rot-reg-bus { qcom,msm-bus,name = "mdss_rot_reg"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <1 590 0 0>, <1 590 0 76800>; }; smmu_rot_unsec: qcom,smmu_rot_unsec_cb { compatible = "qcom,smmu_sde_rot_unsec"; iommus = <&apps_smmu 0x215C 0x0400>; qcom,iommu-dma = "disabled"; }; }; }; Loading
arch/arm64/boot/dts/qcom/kona-sde.dtsi +77 −2 Original line number Diff line number Diff line Loading @@ -7,10 +7,12 @@ compatible = "qcom,sde-kms"; reg = <0x0ae00000 0x84208>, <0x0aeb0000 0x2008>, <0x0aeac000 0x214>; <0x0aeac000 0x214>, <0x0ae8f000 0x02c>; reg-names = "mdp_phys", "vbif_phys", "regdma_phys"; "regdma_phys", "sid_phys"; clocks = <&clock_gcc GCC_DISP_AHB_CLK>, Loading @@ -32,9 +34,15 @@ /* interrupt config */ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <1>; iommus = <&apps_smmu 0x820 0x402>; qcom,iommu-dma = "disabled"; #address-cells = <1>; #size-cells = <0>; #power-domain-cells = <0>; /* hw blocks */ qcom,sde-off = <0x1000>; qcom,sde-len = <0x494>; Loading Loading @@ -301,4 +309,71 @@ <20000 20512 0 6400000>; }; }; mdss_rotator: qcom,mdss_rotator@aea8800 { compatible = "qcom,sde_rotator"; reg = <0x0ae00000 0xac000>, <0x0aeb8000 0x3000>; reg-names = "mdp_phys", "rot_vbif_phys"; #list-cells = <1>; qcom,mdss-rot-mode = <1>; qcom,mdss-highest-bank-bit = <0x3>; /* Bus Scale Settings */ qcom,msm-bus,name = "mdss_rotator"; qcom,msm-bus,num-cases = <3>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <25 512 0 0>, <25 512 0 6400000>, <25 512 0 6400000>; rot-vdd-supply = <&mdss_core_gdsc>; qcom,supply-names = "rot-vdd"; clocks = <&clock_gcc GCC_DISP_AHB_CLK>, <&clock_gcc GCC_DISP_SF_AXI_CLK>, <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, <&clock_dispcc DISP_CC_MDSS_ROT_CLK>; clock-names = "gcc_iface", "gcc_bus", "iface_clk", "rot_clk"; interrupt-parent = <&mdss_mdp>; interrupts = <2 0>; power-domains = <&mdss_mdp>; /* Offline rotator QoS setting */ qcom,mdss-rot-vbif-qos-setting = <3 3 3 3 3 3 3 3>; qcom,mdss-rot-vbif-memtype = <3 3>; qcom,mdss-rot-cdp-setting = <1 1>; qcom,mdss-rot-qos-lut = <0x0 0x0 0x0 0x0>; qcom,mdss-rot-danger-lut = <0x0 0x0>; qcom,mdss-rot-safe-lut = <0x0000ffff 0x0000ffff>; qcom,mdss-default-ot-rd-limit = <32>; qcom,mdss-default-ot-wr-limit = <32>; qcom,mdss-sbuf-headroom = <20>; /* reg bus scale settings */ rot_reg: qcom,rot-reg-bus { qcom,msm-bus,name = "mdss_rot_reg"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <1 590 0 0>, <1 590 0 76800>; }; smmu_rot_unsec: qcom,smmu_rot_unsec_cb { compatible = "qcom,smmu_sde_rot_unsec"; iommus = <&apps_smmu 0x215C 0x0400>; qcom,iommu-dma = "disabled"; }; }; };