stmmac: code tidy-up (ceb69499) · Commits · e / devices / android_kernel_oneplus_sm7250

drivers/net/ethernet/stmicro/stmmac/common.h

+45 −44

Original line number	Diff line number	Diff line
		@@ -182,29 +182,29 @@ struct stmmac_extra_stats {
		#define DMA_HW_FEAT_HDSEL 0x00000004 /* Half-Duplex Support */
		#define DMA_HW_FEAT_EXTHASHEN 0x00000008 /* Expanded DA Hash Filter */
		#define DMA_HW_FEAT_HASHSEL 0x00000010 /* HASH Filter */
		#define DMA_HW_FEAT_ADDMACADRSEL 0x00000020 /* Multiple MAC Addr Reg */
		#define DMA_HW_FEAT_ADDMAC 0x00000020 /* Multiple MAC Addr Reg */
		#define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */
		#define DMA_HW_FEAT_L3L4FLTREN 0x00000080 /* Layer 3 & Layer 4 Feature */
		#define DMA_HW_FEAT_SMASEL 0x00000100 /* SMA(MDIO) Interface */
		#define DMA_HW_FEAT_RWKSEL 0x00000200 /* PMT Remote Wakeup */
		#define DMA_HW_FEAT_MGKSEL 0x00000400 /* PMT Magic Packet */
		#define DMA_HW_FEAT_MMCSEL 0x00000800 /* RMON Module */
		#define DMA_HW_FEAT_TSVER1SEL 0x00001000 /* Only IEEE 1588-2002 Timestamp */
		#define DMA_HW_FEAT_TSVER2SEL 0x00002000 /* IEEE 1588-2008 Adv Timestamp */
		#define DMA_HW_FEAT_TSVER1SEL 0x00001000 /* Only IEEE 1588-2002 */
		#define DMA_HW_FEAT_TSVER2SEL 0x00002000 /* IEEE 1588-2008 PTPv2 */
		#define DMA_HW_FEAT_EEESEL 0x00004000 /* Energy Efficient Ethernet */
		#define DMA_HW_FEAT_AVSEL 0x00008000 /* AV Feature */
		#define DMA_HW_FEAT_TXCOESEL 0x00010000 /* Checksum Offload in Tx */
		#define DMA_HW_FEAT_RXTYP1COE 0x00020000 /* IP csum Offload(Type 1) in Rx */
		#define DMA_HW_FEAT_RXTYP2COE 0x00040000 /* IP csum Offload(Type 2) in Rx */
		#define DMA_HW_FEAT_RXTYP1COE 0x00020000 /* IP COE (Type 1) in Rx */
		#define DMA_HW_FEAT_RXTYP2COE 0x00040000 /* IP COE (Type 2) in Rx */
		#define DMA_HW_FEAT_RXFIFOSIZE 0x00080000 /* Rx FIFO > 2048 Bytes */
		#define DMA_HW_FEAT_RXCHCNT 0x00300000 /* No. of additional Rx Channels */
		#define DMA_HW_FEAT_TXCHCNT 0x00c00000 /* No. of additional Tx Channels */
		#define DMA_HW_FEAT_ENHDESSEL 0x01000000 /* Alternate (Enhanced Descriptor) */
		#define DMA_HW_FEAT_INTTSEN 0x02000000 /* Timestamping with Internal
		System Time */
		#define DMA_HW_FEAT_RXCHCNT 0x00300000 /* No. additional Rx Channels */
		#define DMA_HW_FEAT_TXCHCNT 0x00c00000 /* No. additional Tx Channels */
		#define DMA_HW_FEAT_ENHDESSEL 0x01000000 /* Alternate Descriptor */
		/* Timestamping with Internal System Time */
		#define DMA_HW_FEAT_INTTSEN 0x02000000
		#define DMA_HW_FEAT_FLEXIPPSEN 0x04000000 /* Flexible PPS Output */
		#define DMA_HW_FEAT_SAVLANINS 0x08000000 /* Source Addr or VLAN Insertion */
		#define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY interface */
		#define DMA_HW_FEAT_SAVLANINS 0x08000000 /* Source Addr or VLAN */
		#define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY iface */
		#define DEFAULT_DMA_PBL 8

		/* Max/Min RI Watchdog Timer count value */
		@@ -216,7 +216,8 @@ struct stmmac_extra_stats {
		#define STMMAC_TX_MAX_FRAMES 256
		#define STMMAC_TX_FRAMES 64

		enum rx_frame_status { /* IPC status */
		/* Rx IPC status */
		enum rx_frame_status {
		good_frame = 0,
		discard_frame = 1,
		csum_none = 2,
		@@ -378,7 +379,7 @@ struct stmmac_dma_ops {

		struct stmmac_ops {
		/* MAC core initialization */
		void (core_init) (void __iomem ioaddr) ____cacheline_aligned;
		void (core_init) (void __iomem ioaddr);
		/* Enable and verify that the IPC module is supported */
		int (rx_ipc) (void __iomem ioaddr);
		/* Dump MAC registers */

drivers/net/ethernet/stmicro/stmmac/descs_com.h

+1 −2

Original line number	Diff line number	Diff line
		@@ -117,8 +117,7 @@ static inline void ndesc_rx_set_on_chain(struct dma_desc *p, int end)
		p->des01.rx.second_address_chained = 1;
		}

		static inline void ndesc_tx_set_on_chain(struct dma_desc *p, int
		ring_size)
		static inline void ndesc_tx_set_on_chain(struct dma_desc *p, int ring_size)
		{
		p->des01.tx.second_address_chained = 1;
		}

drivers/net/ethernet/stmicro/stmmac/dwmac1000.h

+34 −35

Original line number	Diff line number	Diff line
		@@ -141,7 +141,7 @@ enum inter_frame_gap {
		GMAC_CONTROL_IFG_80 = 0x00020000,
		GMAC_CONTROL_IFG_40 = 0x000e0000,
		};
		#define GMAC_CONTROL_DCRS 0x00010000 /* Disable carrier sense during tx */
		#define GMAC_CONTROL_DCRS 0x00010000 /* Disable carrier sense */
		#define GMAC_CONTROL_PS 0x00008000 /* Port Select 0:GMI 1:MII */
		#define GMAC_CONTROL_FES 0x00004000 /* Speed 0:10 1:100 */
		#define GMAC_CONTROL_DO 0x00002000 /* Disable Rx Own */
		@@ -150,7 +150,7 @@ enum inter_frame_gap {
		#define GMAC_CONTROL_IPC 0x00000400 /* Checksum Offload */
		#define GMAC_CONTROL_DR 0x00000200 /* Disable Retry */
		#define GMAC_CONTROL_LUD 0x00000100 /* Link up/down */
		#define GMAC_CONTROL_ACS 0x00000080 /* Automatic Pad/FCS Stripping */
		#define GMAC_CONTROL_ACS 0x00000080 /* Auto Pad/FCS Stripping */
		#define GMAC_CONTROL_DC 0x00000010 /* Deferral Check */
		#define GMAC_CONTROL_TE 0x00000008 /* Transmitter Enable */
		#define GMAC_CONTROL_RE 0x00000004 /* Receiver Enable */
		@@ -213,7 +213,8 @@ enum rx_tx_priority_ratio {
		#define DMA_BUS_FB 0x00010000 /* Fixed Burst */

		/* DMA operation mode defines (start/stop tx/rx are placed in common header)*/
		#define DMA_CONTROL_DT 0x04000000 /* Disable Drop TCP/IP csum error */
		/* Disable Drop TCP/IP csum error */
		#define DMA_CONTROL_DT 0x04000000
		#define DMA_CONTROL_RSF 0x02000000 /* Receive Store and Forward */
		#define DMA_CONTROL_DFF 0x01000000 /* Disaable flushing */
		/* Threshold for Activating the FC */
		@@ -264,7 +265,5 @@ enum rtc_control {
		#define GMAC_MMC_TX_INTR 0x108
		#define GMAC_MMC_RX_CSUM_OFFLOAD 0x208



		extern const struct stmmac_dma_ops dwmac1000_dma_ops;
		#endif /* __DWMAC1000_H__ */

drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c

+36 −34

Original line number	Diff line number	Diff line
		@@ -111,12 +111,13 @@ static void dwmac1000_set_filter(struct net_device *dev, int id)
		memset(mc_filter, 0, sizeof(mc_filter));
		netdev_for_each_mc_addr(ha, dev) {
		/* The upper 6 bits of the calculated CRC are used to
		index the contens of the hash table */
		int bit_nr =
		bitrev32(~crc32_le(~0, ha->addr, 6)) >> 26;
		* index the contens of the hash table
		*/
		int bit_nr = bitrev32(~crc32_le(~0, ha->addr, 6)) >> 26;
		/* The most significant bit determines the register to
		* use (H/L) while the other 5 bits determine the bit
		* within the register. */
		* within the register.
		*/
		mc_filter[bit_nr >> 5] \|= 1 << (bit_nr & 31);
		}
		writel(mc_filter[0], ioaddr + GMAC_HASH_LOW);
		@@ -131,8 +132,9 @@ static void dwmac1000_set_filter(struct net_device *dev, int id)

		/* Handle multiple unicast addresses (perfect filtering) */
		if (netdev_uc_count(dev) > perfect_addr_number)
		/* Switch to promiscuous mode is more than 16 addrs
		are required */
		/* Switch to promiscuous mode if more than 16 addrs
		* are required
		*/
		value \|= GMAC_FRAME_FILTER_PR;
		else {
		int reg = 1;
		@@ -150,8 +152,8 @@ static void dwmac1000_set_filter(struct net_device *dev, int id)
		#endif
		writel(value, ioaddr + GMAC_FRAME_FILTER);

		CHIP_DBG(KERN_INFO "\tFrame Filter reg: 0x%08x\n\tHash regs: "
		"HI 0x%08x, LO 0x%08x\n", readl(ioaddr + GMAC_FRAME_FILTER),
		CHIP_DBG(KERN_INFO "\tFilter: 0x%08x\n\tHash: HI 0x%08x, LO 0x%08x\n",
		readl(ioaddr + GMAC_FRAME_FILTER),
		readl(ioaddr + GMAC_HASH_HIGH), readl(ioaddr + GMAC_HASH_LOW));
		}

		@@ -218,8 +220,7 @@ static int dwmac1000_irq_status(void __iomem *ioaddr,
		}
		if (unlikely(intr_status & pmt_irq)) {
		CHIP_DBG(KERN_INFO "GMAC: received Magic frame\n");
		/* clear the PMT bits 5 and 6 by reading the PMT
		* status register. */
		/* clear the PMT bits 5 and 6 by reading the PMT status reg */
		readl(ioaddr + GMAC_PMT);
		x->irq_receive_pmt_irq_n++;
		}
		@@ -287,7 +288,8 @@ static void dwmac1000_set_eee_mode(void __iomem *ioaddr)

		/* Enable the link status receive on RGMII, SGMII ore SMII
		* receive path and instruct the transmit to enter in LPI
		* state. */
		* state.
		*/
		value = readl(ioaddr + LPI_CTRL_STATUS);
		value \|= LPI_CTRL_STATUS_LPIEN \| LPI_CTRL_STATUS_LPITXA;
		writel(value, ioaddr + LPI_CTRL_STATUS);

drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c

+13 −10

Original line number	Diff line number	Diff line
		@@ -94,14 +94,16 @@ static int dwmac1000_dma_init(void __iomem *ioaddr, int pbl, int fb, int mb,
		*
		* For Non Fixed Burst Mode: provide the maximum value of the
		* burst length. Any burst equal or below the provided burst
		* length would be allowed to perform. */
		* length would be allowed to perform.
		*/
		writel(burst_len, ioaddr + DMA_AXI_BUS_MODE);

		/* Mask interrupts by writing to CSR7 */
		writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);

		/* The base address of the RX/TX descriptor lists must be written into
		* DMA CSR3 and CSR4, respectively. */
		/* RX/TX descriptor base address lists must be written into
		* DMA CSR3 and CSR4, respectively
		*/
		writel(dma_tx, ioaddr + DMA_TX_BASE_ADDR);
		writel(dma_rx, ioaddr + DMA_RCV_BASE_ADDR);

		@@ -118,11 +120,12 @@ static void dwmac1000_dma_operation_mode(void __iomem *ioaddr, int txmode,
		/* Transmit COE type 2 cannot be done in cut-through mode. */
		csr6 \|= DMA_CONTROL_TSF;
		/* Operating on second frame increase the performance
		* especially when transmit store-and-forward is used.*/
		* especially when transmit store-and-forward is used.
		*/
		csr6 \|= DMA_CONTROL_OSF;
		} else {
		CHIP_DBG(KERN_DEBUG "GMAC: disabling TX store and forward mode"
		" (threshold = %d)\n", txmode);
		CHIP_DBG(KERN_DEBUG "GMAC: disabling TX SF (threshold %d)\n",
		txmode);
		csr6 &= ~DMA_CONTROL_TSF;
		csr6 &= DMA_CONTROL_TC_TX_MASK;
		/* Set the transmit threshold */
		@@ -142,8 +145,8 @@ static void dwmac1000_dma_operation_mode(void __iomem *ioaddr, int txmode,
		CHIP_DBG(KERN_DEBUG "GMAC: enable RX store and forward mode\n");
		csr6 \|= DMA_CONTROL_RSF;
		} else {
		CHIP_DBG(KERN_DEBUG "GMAC: disabling RX store and forward mode"
		" (threshold = %d)\n", rxmode);
		CHIP_DBG(KERN_DEBUG "GMAC: disable RX SF mode (threshold %d)\n",
		rxmode);
		csr6 &= ~DMA_CONTROL_RSF;
		csr6 &= DMA_CONTROL_TC_RX_MASK;
		if (rxmode <= 32)