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Commit cdcf817b authored by Suzuki K. Poulose's avatar Suzuki K. Poulose Committed by Catalin Marinas
Browse files

arm64: Move mixed endian support detection 



Move the mixed endian support detection code to cpufeature.c
from cpuinfo.c. This also moves the update_cpu_features()
used by mixed endian detection code, which will get more
functionality.

Also moves the ID register field shifts to asm/sysreg.h,
where all the useful definitions will end up in later patches.

Signed-off-by: default avatarSuzuki K. Poulose <suzuki.poulose@arm.com>
Tested-by: default avatarDave Martin <Dave.Martin@arm.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 9cdf8ec4

arch/arm64/include/asm/cpu.h

+2 −0
Original line number Diff line number Diff line
@@ -63,4 +63,6 @@ DECLARE_PER_CPU(struct cpuinfo_arm64, cpu_data); 
void cpuinfo_store_cpu(void);

void __init cpuinfo_store_boot_cpu(void);



void update_cpu_features(struct cpuinfo_arm64 *info);



#endif /* __ASM_CPU_H */

arch/arm64/include/asm/cpufeature.h

+7 −0
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@ 
#define __ASM_CPUFEATURE_H



#include <asm/hwcap.h>

#include <asm/sysreg.h>



/*

 * In the arm64 world (as in the ARM world), elf_hwcap is used both internally
@@ -81,6 +82,12 @@ static inline int __attribute_const__ cpuid_feature_extract_field(u64 features, 
	return (s64)(features << (64 - 4 - field)) >> (64 - 4);

}



static inline bool id_aa64mmfr0_mixed_endian_el0(u64 mmfr0)

{

	return cpuid_feature_extract_field(mmfr0, ID_AA64MMFR0_BIGENDEL_SHIFT) == 0x1 ||

		cpuid_feature_extract_field(mmfr0, ID_AA64MMFR0_BIGENDEL0_SHIFT) == 0x1;

}



void __init setup_cpu_features(void);



void check_cpu_capabilities(const struct arm64_cpu_capabilities *caps,

arch/arm64/include/asm/cputype.h

+0 −15
Original line number Diff line number Diff line
@@ -72,15 +72,6 @@ 


#define APM_CPU_PART_POTENZA	0x000



#define ID_AA64MMFR0_BIGENDEL0_SHIFT	16

#define ID_AA64MMFR0_BIGENDEL0_MASK	(0xf << ID_AA64MMFR0_BIGENDEL0_SHIFT)

#define ID_AA64MMFR0_BIGENDEL0(mmfr0)	\

	(((mmfr0) & ID_AA64MMFR0_BIGENDEL0_MASK) >> ID_AA64MMFR0_BIGENDEL0_SHIFT)

#define ID_AA64MMFR0_BIGEND_SHIFT	8

#define ID_AA64MMFR0_BIGEND_MASK	(0xf << ID_AA64MMFR0_BIGEND_SHIFT)

#define ID_AA64MMFR0_BIGEND(mmfr0)	\

	(((mmfr0) & ID_AA64MMFR0_BIGEND_MASK) >> ID_AA64MMFR0_BIGEND_SHIFT)



#ifndef __ASSEMBLY__



/*
@@ -112,12 +103,6 @@ static inline u32 __attribute_const__ read_cpuid_cachetype(void) 
{

	return read_cpuid(CTR_EL0);

}



static inline bool id_aa64mmfr0_mixed_endian_el0(u64 mmfr0)

{

	return (ID_AA64MMFR0_BIGEND(mmfr0) == 0x1) ||

		(ID_AA64MMFR0_BIGENDEL0(mmfr0) == 0x1);

}

#endif /* __ASSEMBLY__ */



#endif

arch/arm64/include/asm/sysreg.h

+2 −0
Original line number Diff line number Diff line
@@ -44,6 +44,8 @@ 
#define SET_PSTATE_PAN(x) __inst_arm(0xd5000000 | REG_PSTATE_PAN_IMM |\

				     (!!x)<<8 | 0x1f)



#define ID_AA64MMFR0_BIGENDEL0_SHIFT	16

#define ID_AA64MMFR0_BIGENDEL_SHIFT	8



#define ID_AA64MMFR0_TGRAN4_SHIFT	28

#define ID_AA64MMFR0_TGRAN64_SHIFT	24

arch/arm64/kernel/cpufeature.c

+22 −0
Original line number Diff line number Diff line
@@ -22,7 +22,9 @@ 
#include <asm/cpu.h>

#include <asm/cpufeature.h>

#include <asm/processor.h>

#include <asm/sysreg.h>



static bool mixed_endian_el0 = true;

unsigned long elf_hwcap __read_mostly;

EXPORT_SYMBOL_GPL(elf_hwcap);
@@ -41,6 +43,26 @@ unsigned int compat_elf_hwcap2 __read_mostly; 
DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);





bool cpu_supports_mixed_endian_el0(void)

{

	return id_aa64mmfr0_mixed_endian_el0(read_cpuid(ID_AA64MMFR0_EL1));

}



bool system_supports_mixed_endian_el0(void)

{

	return mixed_endian_el0;

}



static void update_mixed_endian_el0_support(struct cpuinfo_arm64 *info)

{

	mixed_endian_el0 &= id_aa64mmfr0_mixed_endian_el0(info->reg_id_aa64mmfr0);

}



void update_cpu_features(struct cpuinfo_arm64 *info)

{

	update_mixed_endian_el0_support(info);

}



static bool

feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)

{