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Commit cd9d1182 authored by Ezequiel Garcia's avatar Ezequiel Garcia Committed by David Woodhouse
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mtd: nand: pxa3xx: Handle ECC and DMA enable/disable properly 



When ECC is not selected, the ECC enable bit must be cleared
in the NAND control register. Same applies to DMA.

Signed-off-by: default avatarEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: default avatarDaniel Mack <zonque@gmail.com>
Signed-off-by: default avatarBrian Norris <computersforpeace@gmail.com>
Signed-off-by: default avatarDavid Woodhouse <David.Woodhouse@intel.com>
parent c0f3b864

drivers/mtd/nand/pxa3xx_nand.c

+11 −2
Original line number Diff line number Diff line
@@ -314,8 +314,17 @@ static void pxa3xx_nand_start(struct pxa3xx_nand_info *info) 
	uint32_t ndcr;



	ndcr = host->reg_ndcr;

	ndcr |= info->use_ecc ? NDCR_ECC_EN : 0;

	ndcr |= info->use_dma ? NDCR_DMA_EN : 0;



	if (info->use_ecc)

		ndcr |= NDCR_ECC_EN;

	else

		ndcr &= ~NDCR_ECC_EN;



	if (info->use_dma)

		ndcr |= NDCR_DMA_EN;

	else

		ndcr &= ~NDCR_DMA_EN;



	ndcr |= NDCR_ND_RUN;



	/* clear status bits and run */