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Commit cd96bea7 authored by Manasi Navare's avatar Manasi Navare Committed by Paulo Zanoni
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drm/i915/icl: Add Voltage swing table for MG PHY DDI Buffer 



This table is used for voltage swing programming sequence during DDI
Buffer initialization for MG PHY DDI Buffers on Icelake.

v2 (from Paulo):
* Fix white space issues.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarManasi Navare <manasi.d.navare@intel.com>
Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180323172419.24911-5-paulo.r.zanoni@intel.com
parent c92f47b5

drivers/gpu/drm/i915/intel_ddi.c

+20 −0
Original line number Diff line number Diff line
@@ -592,6 +592,26 @@ static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_e 
	{ 0x0, 0x00, 0x00 },	/* 350         0.0   */

};



struct icl_mg_phy_ddi_buf_trans {

	u32 cri_txdeemph_override_5_0;

	u32 cri_txdeemph_override_11_6;

	u32 cri_txdeemph_override_17_12;

};



static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = {

				/* Voltage swing  pre-emphasis */

	{ 0x0, 0x1B, 0x00 },	/* 0              0   */

	{ 0x0, 0x23, 0x08 },	/* 0              1   */

	{ 0x0, 0x2D, 0x12 },	/* 0              2   */

	{ 0x0, 0x00, 0x00 },	/* 0              3   */

	{ 0x0, 0x23, 0x00 },	/* 1              0   */

	{ 0x0, 0x2B, 0x09 },	/* 1              1   */

	{ 0x0, 0x2E, 0x11 },	/* 1              2   */

	{ 0x0, 0x2F, 0x00 },	/* 2              0   */

	{ 0x0, 0x33, 0x0C },	/* 2              1   */

	{ 0x0, 0x00, 0x00 },	/* 3              0   */

};



static const struct ddi_buf_trans *

bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)

{