Merge tag 'ep93xx-cleanup' of...

	depends on !ARM_PATCH_PHYS_VIRT

	default DRAM_BASE if !MMU

	default 0x00000000 if ARCH_EBSA110 || \

			EP93XX_SDCE3_SYNC_PHYS_OFFSET || \

			ARCH_FOOTBRIDGE || \

			ARCH_INTEGRATOR || \

			ARCH_IOP13XX || \

	default 0x10000000 if ARCH_OMAP1 || ARCH_RPC

	default 0x20000000 if ARCH_S5PV210

	default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET

	default 0xc0000000 if EP93XX_SDCE0_PHYS_OFFSET || ARCH_SA1100

	default 0xd0000000 if EP93XX_SDCE1_PHYS_OFFSET

	default 0xe0000000 if EP93XX_SDCE2_PHYS_OFFSET

	default 0xf0000000 if EP93XX_SDCE3_ASYNC_PHYS_OFFSET

	default 0xc0000000 if ARCH_SA1100

	help

	  Please provide the physical address corresponding to the

	  location of main memory in your system.

	bool "EP93xx-based"

	select ARCH_HAS_HOLES_MEMORYMODEL

	select ARCH_REQUIRE_GPIOLIB

	select ARCH_USES_GETTIMEOFFSET

	select ARM_AMBA

	select ARM_PATCH_PHYS_VIRT

	select ARM_VIC

	select AUTO_ZRELADDR

	select CLKDEV_LOOKUP

	select CLKSRC_MMIO

	select CPU_ARM920T

	select GENERIC_CLOCKEVENTS

	help

	  This enables support for the Cirrus EP93xx series of CPUs.

comment "EP93xx Platforms"

choice

	prompt "EP93xx first SDRAM bank selection"

	default EP93XX_SDCE3_SYNC_PHYS_OFFSET

config EP93XX_SDCE3_SYNC_PHYS_OFFSET

	bool "0x00000000 - SDCE3/SyncBoot"

	help

	  Select this option if you want support for EP93xx boards with the

	  first SDRAM bank at 0x00000000.

config EP93XX_SDCE0_PHYS_OFFSET

	bool "0xc0000000 - SDCEO"

	help

	  Select this option if you want support for EP93xx boards with the

	  first SDRAM bank at 0xc0000000.

config EP93XX_SDCE1_PHYS_OFFSET

	bool "0xd0000000 - SDCE1"

	help

	  Select this option if you want support for EP93xx boards with the

	  first SDRAM bank at 0xd0000000.

config EP93XX_SDCE2_PHYS_OFFSET

	bool "0xe0000000 - SDCE2"

	help

	  Select this option if you want support for EP93xx boards with the

	  first SDRAM bank at 0xe0000000.

config EP93XX_SDCE3_ASYNC_PHYS_OFFSET

	bool "0xf0000000 - SDCE3/AsyncBoot"

	help

	  Select this option if you want support for EP93xx boards with the

	  first SDRAM bank at 0xf0000000.

endchoice

config MACH_ADSSPHERE

	bool "Support ADS Sphere"

	depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET

	help

	  Say 'Y' here if you want your kernel to support the ADS

	  Sphere board.

config MACH_EDB9301

	bool "Support Cirrus Logic EDB9301"

	depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET

	select MACH_EDB93XX

	help

	  Say 'Y' here if you want your kernel to support the Cirrus

config MACH_EDB9302

	bool "Support Cirrus Logic EDB9302"

	depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET

	select MACH_EDB93XX

	help

	  Say 'Y' here if you want your kernel to support the Cirrus

config MACH_EDB9302A

	bool "Support Cirrus Logic EDB9302A"

	depends on EP93XX_SDCE0_PHYS_OFFSET

	select MACH_EDB93XX

	help

	  Say 'Y' here if you want your kernel to support the Cirrus

config MACH_EDB9307

	bool "Support Cirrus Logic EDB9307"

	depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET

	select MACH_EDB93XX

	help

	  Say 'Y' here if you want your kernel to support the Cirrus

config MACH_EDB9307A

	bool "Support Cirrus Logic EDB9307A"

	depends on EP93XX_SDCE0_PHYS_OFFSET

	select MACH_EDB93XX

	help

	  Say 'Y' here if you want your kernel to support the Cirrus

config MACH_EDB9312

	bool "Support Cirrus Logic EDB9312"

	depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET

	select MACH_EDB93XX

	help

	  Say 'Y' here if you want your kernel to support the Cirrus

config MACH_EDB9315

	bool "Support Cirrus Logic EDB9315"

	depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET

	select MACH_EDB93XX

	help

	  Say 'Y' here if you want your kernel to support the Cirrus

config MACH_EDB9315A

	bool "Support Cirrus Logic EDB9315A"

	depends on EP93XX_SDCE0_PHYS_OFFSET

	select MACH_EDB93XX

	help

	  Say 'Y' here if you want your kernel to support the Cirrus

	  Logic EDB9315A Evaluation Board.

config MACH_GESBC9312

	depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET

	bool "Support Glomation GESBC-9312-sx"

	help

	  Say 'Y' here if you want your kernel to support the Glomation

config MACH_MICRO9H

	bool "Support Contec Micro9-High"

	depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET

	select MACH_MICRO9

	help

	  Say 'Y' here if you want your kernel to support the

config MACH_MICRO9M

	bool "Support Contec Micro9-Mid"

	depends on EP93XX_SDCE3_ASYNC_PHYS_OFFSET

	select MACH_MICRO9

	help

	  Say 'Y' here if you want your kernel to support the

config MACH_MICRO9L

	bool "Support Contec Micro9-Lite"

	depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET

	select MACH_MICRO9

	help

	  Say 'Y' here if you want your kernel to support the

config MACH_MICRO9S

	bool "Support Contec Micro9-Slim"

	depends on EP93XX_SDCE3_ASYNC_PHYS_OFFSET

	select MACH_MICRO9

	help

	  Say 'Y' here if you want your kernel to support the

config MACH_SIM_ONE

        bool "Support Simplemachines Sim.One board"

        depends on EP93XX_SDCE0_PHYS_OFFSET

        help

          Say 'Y' here if you want your kernel to support the

          Simplemachines Sim.One board.

config MACH_SNAPPER_CL15

	bool "Support Bluewater Systems Snapper CL15 Module"

	depends on EP93XX_SDCE0_PHYS_OFFSET

	help

	  Say 'Y' here if you want your kernel to support the Bluewater

	  Systems Snapper CL15 Module.

config MACH_TS72XX

	bool "Support Technologic Systems TS-72xx SBC"

	depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET

	help

	  Say 'Y' here if you want your kernel to support the

	  Technologic Systems TS-72xx board.

config MACH_VISION_EP9307

	bool "Support Vision Engraving Systems EP9307 SoM"

	depends on EP93XX_SDCE0_PHYS_OFFSET

	help

	  Say 'Y' here if you want your kernel to support the

	  Vision Engraving Systems EP9307 SoM.

#

# Makefile for the linux kernel.

#

obj-y			:= core.o clock.o

obj-y			:= core.o clock.o timer-ep93xx.o

obj-$(CONFIG_EP93XX_DMA)	+= dma.o

   zreladdr-$(CONFIG_EP93XX_SDCE3_SYNC_PHYS_OFFSET)	+= 0x00008000

params_phys-$(CONFIG_EP93XX_SDCE3_SYNC_PHYS_OFFSET)	:= 0x00000100

   zreladdr-$(CONFIG_EP93XX_SDCE0_PHYS_OFFSET)		+= 0xc0008000

params_phys-$(CONFIG_EP93XX_SDCE0_PHYS_OFFSET)		:= 0xc0000100

   zreladdr-$(CONFIG_EP93XX_SDCE1_PHYS_OFFSET)		+= 0xd0008000

params_phys-$(CONFIG_EP93XX_SDCE1_PHYS_OFFSET)		:= 0xd0000100

   zreladdr-$(CONFIG_EP93XX_SDCE2_PHYS_OFFSET)		+= 0xe0008000

params_phys-$(CONFIG_EP93XX_SDCE2_PHYS_OFFSET)		:= 0xe0000100

   zreladdr-$(CONFIG_EP93XX_SDCE3_ASYNC_PHYS_OFFSET)	+= 0xf0008000

params_phys-$(CONFIG_EP93XX_SDCE3_ASYNC_PHYS_OFFSET)	:= 0xf0000100

# Empty file waiting for deletion once Makefile.boot isn't needed any more.

#include <linux/interrupt.h>

#include <linux/dma-mapping.h>

#include <linux/sys_soc.h>

#include <linux/timex.h>

#include <linux/irq.h>

#include <linux/io.h>

#include <linux/gpio.h>

#include <linux/irqchip/arm-vic.h>

#include <linux/reboot.h>

#include <linux/usb/ohci_pdriver.h>

#include <linux/random.h>

#include <mach/hardware.h>

#include <linux/platform_data/video-ep93xx.h>

#include <asm/mach/arch.h>

#include <asm/mach/map.h>

#include <asm/mach/time.h>

#include "soc.h"

	iotable_init(ep93xx_io_desc, ARRAY_SIZE(ep93xx_io_desc));

}

/*************************************************************************

 * Timer handling for EP93xx

 *************************************************************************

 * The ep93xx has four internal timers.  Timers 1, 2 (both 16 bit) and

 * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate

 * an interrupt on underflow.  Timer 4 (40 bit) counts down at 983.04 kHz,

 * is free-running, and can't generate interrupts.

 *

 * The 508 kHz timers are ideal for use for the timer interrupt, as the

 * most common values of HZ divide 508 kHz nicely.  We pick one of the 16

 * bit timers (timer 1) since we don't need more than 16 bits of reload

 * value as long as HZ >= 8.

 *

 * The higher clock rate of timer 4 makes it a better choice than the

 * other timers for use in gettimeoffset(), while the fact that it can't

 * generate interrupts means we don't have to worry about not being able

 * to use this timer for something else.  We also use timer 4 for keeping

 * track of lost jiffies.

 */

#define EP93XX_TIMER_REG(x)		(EP93XX_TIMER_BASE + (x))

#define EP93XX_TIMER1_LOAD		EP93XX_TIMER_REG(0x00)

#define EP93XX_TIMER1_VALUE		EP93XX_TIMER_REG(0x04)

#define EP93XX_TIMER1_CONTROL		EP93XX_TIMER_REG(0x08)

#define EP93XX_TIMER123_CONTROL_ENABLE	(1 << 7)

#define EP93XX_TIMER123_CONTROL_MODE	(1 << 6)

#define EP93XX_TIMER123_CONTROL_CLKSEL	(1 << 3)

#define EP93XX_TIMER1_CLEAR		EP93XX_TIMER_REG(0x0c)

#define EP93XX_TIMER2_LOAD		EP93XX_TIMER_REG(0x20)

#define EP93XX_TIMER2_VALUE		EP93XX_TIMER_REG(0x24)

#define EP93XX_TIMER2_CONTROL		EP93XX_TIMER_REG(0x28)

#define EP93XX_TIMER2_CLEAR		EP93XX_TIMER_REG(0x2c)

#define EP93XX_TIMER4_VALUE_LOW		EP93XX_TIMER_REG(0x60)

#define EP93XX_TIMER4_VALUE_HIGH	EP93XX_TIMER_REG(0x64)

#define EP93XX_TIMER4_VALUE_HIGH_ENABLE	(1 << 8)

#define EP93XX_TIMER3_LOAD		EP93XX_TIMER_REG(0x80)

#define EP93XX_TIMER3_VALUE		EP93XX_TIMER_REG(0x84)

#define EP93XX_TIMER3_CONTROL		EP93XX_TIMER_REG(0x88)

#define EP93XX_TIMER3_CLEAR		EP93XX_TIMER_REG(0x8c)

#define EP93XX_TIMER123_CLOCK		508469

#define EP93XX_TIMER4_CLOCK		983040

#define TIMER1_RELOAD			((EP93XX_TIMER123_CLOCK / HZ) - 1)

#define TIMER4_TICKS_PER_JIFFY		DIV_ROUND_CLOSEST(EP93XX_TIMER4_CLOCK, HZ)

static unsigned int last_jiffy_time;

static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id)

{

	/* Writing any value clears the timer interrupt */

	__raw_writel(1, EP93XX_TIMER1_CLEAR);

	/* Recover lost jiffies */

	while ((signed long)

		(__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time)

						>= TIMER4_TICKS_PER_JIFFY) {

		last_jiffy_time += TIMER4_TICKS_PER_JIFFY;

		timer_tick();

	}

	return IRQ_HANDLED;

}

static struct irqaction ep93xx_timer_irq = {

	.name		= "ep93xx timer",

	.flags		= IRQF_TIMER | IRQF_IRQPOLL,

	.handler	= ep93xx_timer_interrupt,

};

static u32 ep93xx_gettimeoffset(void)

{

	int offset;

	offset = __raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time;

	/*

	 * Timer 4 is based on a 983.04 kHz reference clock,

	 * so dividing by 983040 gives the fraction of a second,

	 * so dividing by 0.983040 converts to uS.

	 * Refactor the calculation to avoid overflow.

	 * Finally, multiply by 1000 to give nS.

	 */

	return (offset + (53 * offset / 3072)) * 1000;

}

void __init ep93xx_timer_init(void)

{

	u32 tmode = EP93XX_TIMER123_CONTROL_MODE |

		    EP93XX_TIMER123_CONTROL_CLKSEL;

	arch_gettimeoffset = ep93xx_gettimeoffset;

	/* Enable periodic HZ timer.  */

	__raw_writel(tmode, EP93XX_TIMER1_CONTROL);

	__raw_writel(TIMER1_RELOAD, EP93XX_TIMER1_LOAD);

	__raw_writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE,

			EP93XX_TIMER1_CONTROL);

	/* Enable lost jiffy timer.  */

	__raw_writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE,

			EP93XX_TIMER4_VALUE_HIGH);

	setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq);

}

/*************************************************************************

 * EP93xx IRQ handling

 *************************************************************************/

	if (id != id2)

		return "invalid";

	/* Toss the unique ID into the entropy pool */

	add_device_randomness(&id2, 4);

	add_device_randomness(&id3, 4);

	add_device_randomness(&id4, 4);

	add_device_randomness(&id5, 4);

	snprintf(ep93xx_soc_id, sizeof(ep93xx_soc_id),

		 "%08x%08x%08x%08x", id2, id3, id4, id5);