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Commit cd30798a authored by Zhi Mao's avatar Zhi Mao Committed by Thierry Reding
Browse files

pwm: mediatek: Fix PWM source clock selection 



In original code, the PWM output frequency is not correct when set
bit<3>=1 to PWMCON register.

Signed-off-by: default avatarZhi Mao <zhi.mao@mediatek.com>
Reviewed-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
Acked-by: default avatarJohn Crispin <john@phrozen.org>
Signed-off-by: default avatarThierry Reding <thierry.reding@gmail.com>
parent aa12d7a7

drivers/pwm/pwm-mediatek.c

+1 −1
Original line number Diff line number Diff line
@@ -91,7 +91,7 @@ static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, 
	if (clkdiv > 7)

		return -EINVAL;



	mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | BIT(3) | clkdiv);

	mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv);

	mtk_pwm_writel(pc, pwm->hwpwm, PWMDWIDTH, period_ns / resolution);

	mtk_pwm_writel(pc, pwm->hwpwm, PWMTHRES, duty_ns / resolution);