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Commit cd1182f5 authored by Eric W. Biederman's avatar Eric W. Biederman Committed by Linus Torvalds
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[PATCH] genirq: x86_64 irq: Kill irq compression 



With more irqs in the system we don't need this.

Signed-off-by: default avatarEric W. Biederman <ebiederm@xmission.com>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Rajesh Shah <rajesh.shah@intel.com>
Cc: Andi Kleen <ak@muc.de>
Cc: "Protasevich, Natalie" <Natalie.Protasevich@UNISYS.com>
Cc: "Luck, Tony" <tony.luck@intel.com>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent f023d764

arch/x86_64/kernel/io_apic.c

+0 −5
Original line number Diff line number Diff line
@@ -1415,8 +1415,6 @@ static inline void unlock_ExtINT_logic(void) 
	spin_unlock_irqrestore(&ioapic_lock, flags);

}



int timer_uses_ioapic_pin_0;



/*

 * This code may look a bit paranoid, but it's supposed to cooperate with

 * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
@@ -1453,9 +1451,6 @@ static inline void check_timer(void) 
	pin2  = ioapic_i8259.pin;

	apic2 = ioapic_i8259.apic;



	if (pin1 == 0)

		timer_uses_ioapic_pin_0 = 1;



	apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",

		vector, apic1, pin1, apic2, pin2);

arch/x86_64/kernel/mpparse.c

+1 −41
Original line number Diff line number Diff line
@@ -790,20 +790,11 @@ void __init mp_config_acpi_legacy_irqs(void) 
	}

}



#define MAX_GSI_NUM	4096



int mp_register_gsi(u32 gsi, int triggering, int polarity)

{

	int ioapic = -1;

	int ioapic_pin = 0;

	int idx, bit = 0;

	static int pci_irq = 16;

	/*

	 * Mapping between Global System Interrupts, which

	 * represent all possible interrupts, to the IRQs

	 * assigned to actual devices.

	 */

	static int gsi_to_irq[MAX_GSI_NUM];



	if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC)

		return gsi;
@@ -836,42 +827,11 @@ int mp_register_gsi(u32 gsi, int triggering, int polarity) 
	if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {

		Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",

			mp_ioapic_routing[ioapic].apic_id, ioapic_pin);

		return gsi_to_irq[gsi];

		return gsi;

	}



	mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);



	if (triggering == ACPI_LEVEL_SENSITIVE) {

		/*

		 * For PCI devices assign IRQs in order, avoiding gaps

		 * due to unused I/O APIC pins.

		 */

		int irq = gsi;

		if (gsi < MAX_GSI_NUM) {

			/*

			 * Retain the VIA chipset work-around (gsi > 15), but

			 * avoid a problem where the 8254 timer (IRQ0) is setup

			 * via an override (so it's not on pin 0 of the ioapic),

			 * and at the same time, the pin 0 interrupt is a PCI

			 * type.  The gsi > 15 test could cause these two pins

			 * to be shared as IRQ0, and they are not shareable.

			 * So test for this condition, and if necessary, avoid

			 * the pin collision.

			 */

			if (gsi > 15 || (gsi == 0 && !timer_uses_ioapic_pin_0))

				gsi = pci_irq++;

			/*

			 * Don't assign IRQ used by ACPI SCI

			 */

			if (gsi == acpi_fadt.sci_int)

				gsi = pci_irq++;

			gsi_to_irq[irq] = gsi;

		} else {

			printk(KERN_ERR "GSI %u is too high\n", gsi);

			return gsi;

		}

	}



	io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,

		triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,

		polarity == ACPI_ACTIVE_HIGH ? 0 : 1);

include/asm-x86_64/io_apic.h

+0 −1
Original line number Diff line number Diff line
@@ -162,7 +162,6 @@ extern int skip_ioapic_setup; 
extern int io_apic_get_version (int ioapic);

extern int io_apic_get_redir_entries (int ioapic);

extern int io_apic_set_pci_routing (int ioapic, int pin, int irq, int, int);

extern int timer_uses_ioapic_pin_0;

#endif



extern int sis_apic_bug; /* dummy */