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Commit cce2d453 authored by Yoshinori Sato's avatar Yoshinori Sato Committed by Paul Mundt
Browse files

SH2(A) cache update 



Includes:
- SH2 (7619) Writeback support.
- SH2A cache handling fix.

Signed-off-by: default avatarYoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent 1af446ed

arch/sh/include/cpu-sh2/cpu/cache.h

+4 −2
Original line number Diff line number Diff line
@@ -21,11 +21,11 @@ 
#define CCR		0xffffffec



#define CCR_CACHE_CE	0x01	/* Cache enable */

#define CCR_CACHE_WT	0x06    /* CCR[bit1=1,bit2=1] */

#define CCR_CACHE_WT	0x02    /* CCR[bit1=1,bit2=1] */

				/* 0x00000000-0x7fffffff: Write-through  */

				/* 0x80000000-0x9fffffff: Write-back     */

                                /* 0xc0000000-0xdfffffff: Write-through  */

#define CCR_CACHE_CB	0x00    /* CCR[bit1=0,bit2=0] */

#define CCR_CACHE_CB	0x04    /* CCR[bit1=0,bit2=0] */

				/* 0x00000000-0x7fffffff: Write-back     */

				/* 0x80000000-0x9fffffff: Write-through  */

                                /* 0xc0000000-0xdfffffff: Write-back     */
@@ -36,6 +36,8 @@ 


#define CCR_CACHE_ENABLE	CCR_CACHE_CE

#define CCR_CACHE_INVALIDATE	CCR_CACHE_CF

#define CACHE_PHYSADDR_MASK	0x1ffffc00



#endif



#endif /* __ASM_CPU_SH2_CACHE_H */

arch/sh/include/cpu-sh2a/cpu/cache.h

+3 −0
Original line number Diff line number Diff line
@@ -36,5 +36,8 @@ 


#define CCR_CACHE_ENABLE	(CCR_CACHE_OCE | CCR_CACHE_ICE)

#define CCR_CACHE_INVALIDATE	(CCR_CACHE_OCI | CCR_CACHE_ICI)

#define CCR_ICACHE_INVALIDATE	CCR_CACHE_ICI

#define CCR_OCACHE_INVALIDATE	CCR_CACHE_OCI

#define CACHE_PHYSADDR_MASK	0x1ffffc00



#endif /* __ASM_CPU_SH2A_CACHE_H */

arch/sh/include/cpu-sh2a/cpu/cacheflush.h

0 → 100644
+34 −0
Original line number Diff line number Diff line 
#ifndef __ASM_CPU_SH2A_CACHEFLUSH_H

#define __ASM_CPU_SH2A_CACHEFLUSH_H



/* 

 * Cache flushing:

 *

 *  - flush_cache_all() flushes entire cache

 *  - flush_cache_mm(mm) flushes the specified mm context's cache lines

 *  - flush_cache_dup mm(mm) handles cache flushing when forking

 *  - flush_cache_page(mm, vmaddr, pfn) flushes a single page

 *  - flush_cache_range(vma, start, end) flushes a range of pages

 *

 *  - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache

 *  - flush_icache_range(start, end) flushes(invalidates) a range for icache

 *  - flush_icache_page(vma, pg) flushes(invalidates) a page for icache

 *

 *  Caches are indexed (effectively) by physical address on SH-2, so

 *  we don't need them.

 */

#define flush_cache_all()			do { } while (0)

#define flush_cache_mm(mm)			do { } while (0)

#define flush_cache_dup_mm(mm)			do { } while (0)

#define flush_cache_range(vma, start, end)	do { } while (0)

#define flush_cache_page(vma, vmaddr, pfn)	do { } while (0)

#define flush_dcache_page(page)			do { } while (0)

#define flush_dcache_mmap_lock(mapping)		do { } while (0)

#define flush_dcache_mmap_unlock(mapping)	do { } while (0)

void flush_icache_range(unsigned long start, unsigned long end);

#define flush_icache_page(vma,pg)		do { } while (0)

#define flush_icache_user_range(vma,pg,adr,len)	do { } while (0)

#define flush_cache_sigtramp(vaddr)		do { } while (0)



#define p3_cache_init()				do { } while (0)

#endif /* __ASM_CPU_SH2A_CACHEFLUSH_H */

arch/sh/mm/Kconfig

+0 −1
Original line number Diff line number Diff line
@@ -237,7 +237,6 @@ choice 


config CACHE_WRITEBACK

	bool "Write-back"

	depends on CPU_SH2A || CPU_SH3 || CPU_SH4 || CPU_SH5



config CACHE_WRITETHROUGH

	bool "Write-through"

arch/sh/mm/Makefile_32

+7 −4
Original line number Diff line number Diff line
@@ -5,12 +5,15 @@ 
obj-y			:= init.o extable_32.o consistent.o



ifndef CONFIG_CACHE_OFF

obj-$(CONFIG_CPU_SH2)		+= cache-sh2.o

obj-$(CONFIG_CPU_SH3)		+= cache-sh3.o

obj-$(CONFIG_CPU_SH4)		+= cache-sh4.o

obj-$(CONFIG_SH7705_CACHE_32KB)	+= cache-sh7705.o

cache-$(CONFIG_CPU_SH2)		:= cache-sh2.o

cache-$(CONFIG_CPU_SH2A)	:= cache-sh2a.o

cache-$(CONFIG_CPU_SH3)		:= cache-sh3.o

cache-$(CONFIG_CPU_SH4)		:= cache-sh4.o

cache-$(CONFIG_SH7705_CACHE_32KB)	+= cache-sh7705.o

endif



obj-y			+= $(cache-y)



mmu-y			:= tlb-nommu.o pg-nommu.o

mmu-$(CONFIG_MMU)	:= fault_32.o tlbflush_32.o ioremap_32.o