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Commit cc9b0918 authored by Viresh Kumar's avatar Viresh Kumar Committed by Heiko Stuebner
Browse files

arm64: dts: rockchip: Add missing cooling device properties for CPUs 



The cooling device properties, like "#cooling-cells" and
"dynamic-power-coefficient", should either be present for all the CPUs
of a cluster or none. If these are present only for a subset of CPUs of
a cluster then things will start falling apart as soon as the CPUs are
brought online in a different order. For example, this will happen
because the operating system looks for such properties in the CPU node
it is trying to bring up, so that it can register a cooling device.

Add such missing properties.

Do minor rearrangement as well to keep ordering consistent.

Signed-off-by: default avatarViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent ea41d63b

arch/arm64/boot/dts/rockchip/rk3328.dtsi

+3 −0
Original line number Diff line number Diff line
@@ -52,6 +52,7 @@ 
			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0x0 0x1>;

			clocks = <&cru ARMCLK>;

			#cooling-cells = <2>;

			dynamic-power-coefficient = <120>;

			enable-method = "psci";

			next-level-cache = <&l2>;
@@ -63,6 +64,7 @@ 
			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0x0 0x2>;

			clocks = <&cru ARMCLK>;

			#cooling-cells = <2>;

			dynamic-power-coefficient = <120>;

			enable-method = "psci";

			next-level-cache = <&l2>;
@@ -74,6 +76,7 @@ 
			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0x0 0x3>;

			clocks = <&cru ARMCLK>;

			#cooling-cells = <2>;

			dynamic-power-coefficient = <120>;

			enable-method = "psci";

			next-level-cache = <&l2>;

arch/arm64/boot/dts/rockchip/rk3368.dtsi

+6 −2
Original line number Diff line number Diff line
@@ -76,7 +76,6 @@ 
			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0x0 0x0>;

			enable-method = "psci";



			#cooling-cells = <2>; /* min followed by max */

		};
@@ -85,6 +84,7 @@ 
			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0x0 0x1>;

			enable-method = "psci";

			#cooling-cells = <2>; /* min followed by max */

		};



		cpu_l2: cpu@2 {
@@ -92,6 +92,7 @@ 
			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0x0 0x2>;

			enable-method = "psci";

			#cooling-cells = <2>; /* min followed by max */

		};



		cpu_l3: cpu@3 {
@@ -99,6 +100,7 @@ 
			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0x0 0x3>;

			enable-method = "psci";

			#cooling-cells = <2>; /* min followed by max */

		};



		cpu_b0: cpu@100 {
@@ -106,7 +108,6 @@ 
			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0x0 0x100>;

			enable-method = "psci";



			#cooling-cells = <2>; /* min followed by max */

		};
@@ -115,6 +116,7 @@ 
			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0x0 0x101>;

			enable-method = "psci";

			#cooling-cells = <2>; /* min followed by max */

		};



		cpu_b2: cpu@102 {
@@ -122,6 +124,7 @@ 
			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0x0 0x102>;

			enable-method = "psci";

			#cooling-cells = <2>; /* min followed by max */

		};



		cpu_b3: cpu@103 {
@@ -129,6 +132,7 @@ 
			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0x0 0x103>;

			enable-method = "psci";

			#cooling-cells = <2>; /* min followed by max */

		};

	};

arch/arm64/boot/dts/rockchip/rk3399.dtsi

+6 −2
Original line number Diff line number Diff line
@@ -71,8 +71,8 @@ 
			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0x0 0x0>;

			enable-method = "psci";

			#cooling-cells = <2>; /* min followed by max */

			clocks = <&cru ARMCLKL>;

			#cooling-cells = <2>; /* min followed by max */

			dynamic-power-coefficient = <100>;

		};
@@ -82,6 +82,7 @@ 
			reg = <0x0 0x1>;

			enable-method = "psci";

			clocks = <&cru ARMCLKL>;

			#cooling-cells = <2>; /* min followed by max */

			dynamic-power-coefficient = <100>;

		};
@@ -91,6 +92,7 @@ 
			reg = <0x0 0x2>;

			enable-method = "psci";

			clocks = <&cru ARMCLKL>;

			#cooling-cells = <2>; /* min followed by max */

			dynamic-power-coefficient = <100>;

		};
@@ -100,6 +102,7 @@ 
			reg = <0x0 0x3>;

			enable-method = "psci";

			clocks = <&cru ARMCLKL>;

			#cooling-cells = <2>; /* min followed by max */

			dynamic-power-coefficient = <100>;

		};
@@ -108,8 +111,8 @@ 
			compatible = "arm,cortex-a72", "arm,armv8";

			reg = <0x0 0x100>;

			enable-method = "psci";

			#cooling-cells = <2>; /* min followed by max */

			clocks = <&cru ARMCLKB>;

			#cooling-cells = <2>; /* min followed by max */

			dynamic-power-coefficient = <436>;

		};
@@ -119,6 +122,7 @@ 
			reg = <0x0 0x101>;

			enable-method = "psci";

			clocks = <&cru ARMCLKB>;

			#cooling-cells = <2>; /* min followed by max */

			dynamic-power-coefficient = <436>;

		};

	};