Loading drivers/iommu/arm-smmu.c +10 −9 Original line number Diff line number Diff line Loading @@ -86,7 +86,7 @@ #define ARM_MMU500_ACR_SMTNMB_TLBEN (1 << 8) #define TLB_LOOP_TIMEOUT 500000 /* 500ms */ #define TLB_SPIN_COUNT 10 #define TLB_LOOP_INC_MAX 1000 /*1ms*/ #define ARM_SMMU_IMPL_DEF0(smmu) \ ((smmu)->base + (2 * (1 << (smmu)->pgshift))) Loading Loading @@ -1280,16 +1280,17 @@ static void __arm_smmu_tlb_sync_timeout(struct arm_smmu_device *smmu) static int __arm_smmu_tlb_sync(struct arm_smmu_device *smmu, void __iomem *sync, void __iomem *status) { unsigned int spin_cnt, delay; unsigned int inc, delay; writel_relaxed(QCOM_DUMMY_VAL, sync); for (delay = 1; delay < TLB_LOOP_TIMEOUT; delay *= 2) { for (spin_cnt = TLB_SPIN_COUNT; spin_cnt > 0; spin_cnt--) { for (delay = 1, inc = 1; delay < TLB_LOOP_TIMEOUT; delay += inc) { if (!(readl_relaxed(status) & sTLBGSTATUS_GSACTIVE)) return 0; cpu_relax(); } udelay(delay); udelay(inc); if (inc < TLB_LOOP_INC_MAX) inc *= 2; } trace_tlbsync_timeout(smmu->dev, 0); __arm_smmu_tlb_sync_timeout(smmu); Loading Loading
drivers/iommu/arm-smmu.c +10 −9 Original line number Diff line number Diff line Loading @@ -86,7 +86,7 @@ #define ARM_MMU500_ACR_SMTNMB_TLBEN (1 << 8) #define TLB_LOOP_TIMEOUT 500000 /* 500ms */ #define TLB_SPIN_COUNT 10 #define TLB_LOOP_INC_MAX 1000 /*1ms*/ #define ARM_SMMU_IMPL_DEF0(smmu) \ ((smmu)->base + (2 * (1 << (smmu)->pgshift))) Loading Loading @@ -1280,16 +1280,17 @@ static void __arm_smmu_tlb_sync_timeout(struct arm_smmu_device *smmu) static int __arm_smmu_tlb_sync(struct arm_smmu_device *smmu, void __iomem *sync, void __iomem *status) { unsigned int spin_cnt, delay; unsigned int inc, delay; writel_relaxed(QCOM_DUMMY_VAL, sync); for (delay = 1; delay < TLB_LOOP_TIMEOUT; delay *= 2) { for (spin_cnt = TLB_SPIN_COUNT; spin_cnt > 0; spin_cnt--) { for (delay = 1, inc = 1; delay < TLB_LOOP_TIMEOUT; delay += inc) { if (!(readl_relaxed(status) & sTLBGSTATUS_GSACTIVE)) return 0; cpu_relax(); } udelay(delay); udelay(inc); if (inc < TLB_LOOP_INC_MAX) inc *= 2; } trace_tlbsync_timeout(smmu->dev, 0); __arm_smmu_tlb_sync_timeout(smmu); Loading