Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit cc3f90f0 authored by Ander Conselvan de Oliveira's avatar Ander Conselvan de Oliveira
Browse files

drm/i915/glk: Reuse broxton code for geminilake 



Geminilake is mostly backwards compatible with broxton, so change most
of the IS_BROXTON() checks to IS_GEN9_LP(). Differences between the
platforms will be implemented in follow-up patches.

v2: Don't reuse broxton's path in intel_update_max_cdclk().
    Don't set plane count as in broxton.

v3: Rebase

v4: Include the check intel_bios_is_port_hpd_inverted().
    Commit message.

v5: Leave i915_dmc_info() out; glk's csr version != bxt's. (Rodrigo)

v6: Rebase.

v7: Convert a few mode IS_BROXTON() occurances in pps, ddi, dsi and pll
    code. (Rodrigo)

v8: Squash a couple of DDI patches with more conversions. (Rodrigo)

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1480667037-11215-2-git-send-email-ander.conselvan.de.oliveira@intel.com
parent 8bf41b72

drivers/gpu/drm/i915/i915_debugfs.c

+5 −5
Original line number Diff line number Diff line
@@ -1108,7 +1108,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused) 
		int max_freq;



		rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);

		if (IS_BROXTON(dev_priv)) {

		if (IS_GEN9_LP(dev_priv)) {

			rp_state_cap = I915_READ(BXT_RP_STATE_CAP);

			gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);

		} else {
@@ -1204,7 +1204,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused) 
		seq_printf(m, "Down threshold: %d%%\n",

			   dev_priv->rps.down_threshold);



		max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 0 :

		max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :

			    rp_state_cap >> 16) & 0xff;

		max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?

			     GEN9_FREQ_SCALER : 1);
@@ -1217,7 +1217,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused) 
		seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",

			   intel_gpu_freq(dev_priv, max_freq));



		max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 16 :

		max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :

			    rp_state_cap >> 0) & 0xff;

		max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?

			     GEN9_FREQ_SCALER : 1);
@@ -5180,7 +5180,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, 
	u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];



	/* BXT has a single slice and at most 3 subslices. */

	if (IS_BROXTON(dev_priv)) {

	if (IS_GEN9_LP(dev_priv)) {

		s_max = 1;

		ss_max = 3;

	}
@@ -5214,7 +5214,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, 
		for (ss = 0; ss < ss_max; ss++) {

			unsigned int eu_cnt;



			if (IS_BROXTON(dev_priv)) {

			if (IS_GEN9_LP(dev_priv)) {

				if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))

					/* skip disabled subslice */

					continue;

drivers/gpu/drm/i915/i915_gem_gtt.c

+4 −4
Original line number Diff line number Diff line
@@ -372,7 +372,7 @@ static void kunmap_page_dma(struct drm_i915_private *dev_priv, void *vaddr) 
	/* There are only few exceptions for gen >=6. chv and bxt.

	 * And we are not sure about the latter so play safe for now.

	 */

	if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))

	if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))

		drm_clflush_virt_range(vaddr, PAGE_SIZE);



	kunmap_atomic(vaddr);
@@ -2939,7 +2939,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size) 
	 * resort to an uncached mapping. The WC issue is easily caught by the

	 * readback check when writing GTT PTE entries.

	 */

	if (IS_BROXTON(dev_priv))

	if (IS_GEN9_LP(dev_priv))

		ggtt->gsm = ioremap_nocache(phys_addr, size);

	else

		ggtt->gsm = ioremap_wc(phys_addr, size);
@@ -3069,7 +3069,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt) 


	ggtt->base.total = (size / sizeof(gen8_pte_t)) << PAGE_SHIFT;



	if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))

	if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))

		chv_setup_private_ppat(dev_priv);

	else

		bdw_setup_private_ppat(dev_priv);
@@ -3309,7 +3309,7 @@ void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv) 
	ggtt->base.closed = false;



	if (INTEL_GEN(dev_priv) >= 8) {

		if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))

		if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))

			chv_setup_private_ppat(dev_priv);

		else

			bdw_setup_private_ppat(dev_priv);

drivers/gpu/drm/i915/i915_irq.c

+5 −5
Original line number Diff line number Diff line
@@ -2435,7 +2435,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) 
				found = true;

			}



			if (IS_BROXTON(dev_priv)) {

			if (IS_GEN9_LP(dev_priv)) {

				tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;

				if (tmp_mask) {

					bxt_hpd_irq_handler(dev_priv, tmp_mask,
@@ -2451,7 +2451,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) 
				}

			}



			if (IS_BROXTON(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {

			if (IS_GEN9_LP(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {

				gmbus_irq_handler(dev_priv);

				found = true;

			}
@@ -3375,7 +3375,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) 
				  GEN9_DE_PIPE_IRQ_FAULT_ERRORS;

		de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |

				  GEN9_AUX_CHANNEL_D;

		if (IS_BROXTON(dev_priv))

		if (IS_GEN9_LP(dev_priv))

			de_port_masked |= BXT_DE_PORT_GMBUS;

	} else {

		de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
@@ -3386,7 +3386,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) 
					   GEN8_PIPE_FIFO_UNDERRUN;



	de_port_enables = de_port_masked;

	if (IS_BROXTON(dev_priv))

	if (IS_GEN9_LP(dev_priv))

		de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;

	else if (IS_BROADWELL(dev_priv))

		de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
@@ -4211,7 +4211,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv) 
		dev->driver->irq_uninstall = gen8_irq_uninstall;

		dev->driver->enable_vblank = gen8_enable_vblank;

		dev->driver->disable_vblank = gen8_disable_vblank;

		if (IS_BROXTON(dev_priv))

		if (IS_GEN9_LP(dev_priv))

			dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;

		else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))

			dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;

drivers/gpu/drm/i915/i915_reg.h

+2 −2
Original line number Diff line number Diff line
@@ -3256,7 +3256,7 @@ enum skl_disp_power_wells { 
#define INTERVAL_1_33_US(us)	(((us) * 3)   >> 2)

#define INTERVAL_0_833_US(us)	(((us) * 6) / 5)

#define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN9(dev_priv) ? \

				(IS_BROXTON(dev_priv) ? \

				(IS_GEN9_LP(dev_priv) ? \

				INTERVAL_0_833_US(us) : \

				INTERVAL_1_33_US(us)) : \

				INTERVAL_1_28_US(us))
@@ -3265,7 +3265,7 @@ enum skl_disp_power_wells { 
#define INTERVAL_1_33_TO_US(interval)  (((interval) << 2) / 3)

#define INTERVAL_0_833_TO_US(interval) (((interval) * 5)  / 6)

#define GT_PM_INTERVAL_TO_US(dev_priv, interval) (IS_GEN9(dev_priv) ? \

                           (IS_BROXTON(dev_priv) ? \

                           (IS_GEN9_LP(dev_priv) ? \

                           INTERVAL_0_833_TO_US(interval) : \

                           INTERVAL_1_33_TO_US(interval)) : \

                           INTERVAL_1_28_TO_US(interval))

drivers/gpu/drm/i915/intel_bios.c

+1 −1
Original line number Diff line number Diff line
@@ -1779,7 +1779,7 @@ intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv, 
{

	int i;



	if (WARN_ON_ONCE(!IS_BROXTON(dev_priv)))

	if (WARN_ON_ONCE(!IS_GEN9_LP(dev_priv)))

		return false;



	for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {