Merge "clk: qcom: clk-alpha-pll: Update the list_registers ops for all PLLs" (cbf04cca) · Commits · e / devices / android_kernel_oneplus_sm7250

drivers/clk/qcom/clk-alpha-pll.c

+48 −41

Original line number	Diff line number	Diff line
		@@ -844,12 +844,16 @@ static void clk_alpha_pll_list_registers(struct seq_file f, struct clk_hw hw)
		int size, i, val;

		static struct clk_register_data data[] = {
		{"PLL_MODE", 0x0},
		{"PLL_L_VAL", 0x4},
		{"PLL_ALPHA_VAL", 0x8},
		{"PLL_ALPHA_VAL_U", 0xC},
		{"PLL_USER_CTL", 0x10},
		{"PLL_CONFIG_CTL", 0x18},
		{"PLL_MODE", PLL_OFF_MODE},
		{"PLL_L_VAL", PLL_OFF_L_VAL},
		{"PLL_ALPHA_VAL", PLL_OFF_ALPHA_VAL},
		{"PLL_ALPHA_VAL_U", PLL_OFF_ALPHA_VAL_U},
		{"PLL_TEST_CTL", PLL_OFF_TEST_CTL},
		{"PLL_TEST_CTL_U", PLL_OFF_TEST_CTL_U},
		{"PLL_USER_CTL", PLL_OFF_USER_CTL},
		{"PLL_USER_CTL_U", PLL_OFF_USER_CTL_U},
		{"PLL_CONFIG_CTL", PLL_OFF_CONFIG_CTL},
		{"PLL_STATUS", PLL_OFF_STATUS},
		};

		static struct clk_register_data data1[] = {
		@@ -859,13 +863,14 @@ static void clk_alpha_pll_list_registers(struct seq_file f, struct clk_hw hw)
		size = ARRAY_SIZE(data);

		for (i = 0; i < size; i++) {
		regmap_read(pll->clkr.regmap, pll->offset + data[i].offset,
		&val);
		regmap_read(pll->clkr.regmap,
		pll->offset + pll->regs[data[i].offset], &val);
		clock_debug_output(f, false,
		"%20s: 0x%.8x\n", data[i].name, val);
		}

		regmap_read(pll->clkr.regmap, pll->offset + data[0].offset, &val);
		regmap_read(pll->clkr.regmap, pll->offset +
		pll->regs[data[0].offset], &val);

		if (val & PLL_FSM_ENA) {
		regmap_read(pll->clkr.regmap, pll->clkr.enable_reg +
		@@ -1125,18 +1130,18 @@ static void clk_zonda_pll_list_registers(struct seq_file f, struct clk_hw hw)
		int size, i, val;

		static struct clk_register_data pll_regs[] = {
		{"PLL_MODE", 0x0},
		{"PLL_L_VAL", 0x4},
		{"PLL_ALPHA_VAL", 0x8},
		{"PLL_USER_CTL", 0xC},
		{"PLL_CONFIG_CTL", 0x10},
		{"PLL_CONFIG_CTL_U", 0x14},
		{"PLL_CONFIG_CTL_U1", 0x18},
		{"PLL_TEST_CTL", 0x1C},
		{"PLL_TEST_CTL_U", 0x20},
		{"PLL_TEST_CTL_U1", 0x24},
		{"PLL_OPMODE", 0x28},
		{"PLL_STATUS", 0x38},
		{"PLL_MODE", PLL_OFF_MODE},
		{"PLL_L_VAL", PLL_OFF_L_VAL},
		{"PLL_ALPHA_VAL", PLL_OFF_ALPHA_VAL},
		{"PLL_USER_CTL", PLL_OFF_USER_CTL},
		{"PLL_CONFIG_CTL", PLL_OFF_CONFIG_CTL},
		{"PLL_CONFIG_CTL_U", PLL_OFF_CONFIG_CTL_U},
		{"PLL_CONFIG_CTL_U1", PLL_OFF_CONFIG_CTL_U1},
		{"PLL_TEST_CTL", PLL_OFF_TEST_CTL},
		{"PLL_TEST_CTL_U", PLL_OFF_TEST_CTL_U},
		{"PLL_TEST_CTL_U1", PLL_OFF_TEST_CTL_U1},
		{"PLL_OPMODE", PLL_OFF_OPMODE},
		{"PLL_STATUS", PLL_OFF_STATUS},
		};

		static struct clk_register_data pll_vote_reg = {
		@@ -1146,13 +1151,14 @@ static void clk_zonda_pll_list_registers(struct seq_file f, struct clk_hw hw)
		size = ARRAY_SIZE(pll_regs);

		for (i = 0; i < size; i++) {
		regmap_read(pll->clkr.regmap, pll->offset + pll_regs[i].offset,
		&val);
		regmap_read(pll->clkr.regmap, pll->offset +
		pll->regs[pll_regs[i].offset], &val);
		clock_debug_output(f, false,
		"%20s: 0x%.8x\n", pll_regs[i].name, val);
		}

		regmap_read(pll->clkr.regmap, pll->offset + pll_vote_reg.offset, &val);
		regmap_read(pll->clkr.regmap, pll->offset +
		pll->regs[pll_regs[0].offset], &val);

		if (val & PLL_FSM_ENA) {
		regmap_read(pll->clkr.regmap, pll->clkr.enable_reg +
		@@ -1894,20 +1900,20 @@ static void clk_alpha_pll_lucid_list_registers(struct seq_file *f,
		int size, i, val;

		static struct clk_register_data data[] = {
		{"PLL_MODE", 0x0},
		{"PLL_L_VAL", 0x4},
		{"PLL_CAL_L_VAL", 0x8},
		{"PLL_USER_CTL", 0x0c},
		{"PLL_USER_CTL_U", 0x10},
		{"PLL_USER_CTL_U1", 0x14},
		{"PLL_CONFIG_CTL", 0x18},
		{"PLL_CONFIG_CTL_U", 0x1c},
		{"PLL_CONFIG_CTL_U1", 0x20},
		{"PLL_TEST_CTL", 0x24},
		{"PLL_TEST_CTL_U", 0x28},
		{"PLL_TEST_CTL_U1", 0x2C},
		{"PLL_STATUS", 0x30},
		{"PLL_ALPHA_VAL", 0x40},
		{"PLL_MODE", PLL_OFF_MODE},
		{"PLL_L_VAL", PLL_OFF_L_VAL},
		{"PLL_CAL_L_VAL", PLL_OFF_CAL_L_VAL},
		{"PLL_USER_CTL", PLL_OFF_USER_CTL},
		{"PLL_USER_CTL_U", PLL_OFF_USER_CTL_U},
		{"PLL_USER_CTL_U1", PLL_OFF_USER_CTL_U1},
		{"PLL_CONFIG_CTL", PLL_OFF_CONFIG_CTL},
		{"PLL_CONFIG_CTL_U", PLL_OFF_CONFIG_CTL_U},
		{"PLL_CONFIG_CTL_U1", PLL_OFF_CONFIG_CTL_U1},
		{"PLL_TEST_CTL", PLL_OFF_TEST_CTL},
		{"PLL_TEST_CTL_U", PLL_OFF_TEST_CTL_U},
		{"PLL_TEST_CTL_U1", PLL_OFF_TEST_CTL_U1},
		{"PLL_STATUS", PLL_OFF_STATUS},
		{"PLL_ALPHA_VAL", PLL_OFF_ALPHA_VAL},
		};

		static struct clk_register_data data1[] = {
		@@ -1917,13 +1923,14 @@ static void clk_alpha_pll_lucid_list_registers(struct seq_file *f,
		size = ARRAY_SIZE(data);

		for (i = 0; i < size; i++) {
		regmap_read(pll->clkr.regmap, pll->offset + data[i].offset,
		&val);
		regmap_read(pll->clkr.regmap, pll->offset +
		pll->regs[data[i].offset], &val);
		clock_debug_output(f, false,
		"%20s: 0x%.8x\n", data[i].name, val);
		}

		regmap_read(pll->clkr.regmap, pll->offset + data[0].offset, &val);
		regmap_read(pll->clkr.regmap, pll->offset +
		pll->regs[data[0].offset], &val);

		if (val & PLL_FSM_ENA) {
		regmap_read(pll->clkr.regmap, pll->clkr.enable_reg +

drivers/clk/qcom/clk-alpha-pll.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -19,6 +19,7 @@ enum {
		};

		enum {
		PLL_OFF_MODE,
		PLL_OFF_L_VAL,
		PLL_OFF_CAL_L_VAL,
		PLL_OFF_ALPHA_VAL,