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Commit cbe6dd01 authored by Smitha T Murthy's avatar Smitha T Murthy Committed by Greg Kroah-Hartman
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media: s5p-mfc: Fix in register read and write for H264 



[ Upstream commit 06710cd5d2436135046898d7e4b9408c8bb99446 ]

Few of the H264 encoder registers written were not getting reflected
since the read values were not stored and getting overwritten.

Fixes: 6a9c6f68 ("[media] s5p-mfc: Add variants to access mfc registers")

Cc: stable@vger.kernel.org
Cc: linux-fsd@tesla.com
Signed-off-by: default avatarSmitha T Murthy <smitha.t@samsung.com>
Signed-off-by: default avatarHans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent 12242bd1

drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c

+7 −7
Original line number Diff line number Diff line
@@ -1063,7 +1063,7 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx) 
	}



	/* aspect ratio VUI */

	readl(mfc_regs->e_h264_options);

	reg = readl(mfc_regs->e_h264_options);

	reg &= ~(0x1 << 5);

	reg |= ((p_h264->vui_sar & 0x1) << 5);

	writel(reg, mfc_regs->e_h264_options);
@@ -1086,7 +1086,7 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx) 


	/* intra picture period for H.264 open GOP */

	/* control */

	readl(mfc_regs->e_h264_options);

	reg = readl(mfc_regs->e_h264_options);

	reg &= ~(0x1 << 4);

	reg |= ((p_h264->open_gop & 0x1) << 4);

	writel(reg, mfc_regs->e_h264_options);
@@ -1100,23 +1100,23 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx) 
	}



	/* 'WEIGHTED_BI_PREDICTION' for B is disable */

	readl(mfc_regs->e_h264_options);

	reg = readl(mfc_regs->e_h264_options);

	reg &= ~(0x3 << 9);

	writel(reg, mfc_regs->e_h264_options);



	/* 'CONSTRAINED_INTRA_PRED_ENABLE' is disable */

	readl(mfc_regs->e_h264_options);

	reg = readl(mfc_regs->e_h264_options);

	reg &= ~(0x1 << 14);

	writel(reg, mfc_regs->e_h264_options);



	/* ASO */

	readl(mfc_regs->e_h264_options);

	reg = readl(mfc_regs->e_h264_options);

	reg &= ~(0x1 << 6);

	reg |= ((p_h264->aso & 0x1) << 6);

	writel(reg, mfc_regs->e_h264_options);



	/* hier qp enable */

	readl(mfc_regs->e_h264_options);

	reg = readl(mfc_regs->e_h264_options);

	reg &= ~(0x1 << 8);

	reg |= ((p_h264->open_gop & 0x1) << 8);

	writel(reg, mfc_regs->e_h264_options);
@@ -1137,7 +1137,7 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx) 
	writel(reg, mfc_regs->e_h264_num_t_layer);



	/* frame packing SEI generation */

	readl(mfc_regs->e_h264_options);

	reg = readl(mfc_regs->e_h264_options);

	reg &= ~(0x1 << 25);

	reg |= ((p_h264->sei_frame_packing & 0x1) << 25);

	writel(reg, mfc_regs->e_h264_options);